75217521Plus / N N/B MAINTENANCEPlus / N N/B MAINTENANCE
5. Pin Descriptions Of Major Components
5.1 Pentium III/Celeron FC-PGA2 CPU
PWRGOOD Relationship at Power On
Signal NameI/OSignal DescriptionSignal NameI/OSignal Description
RSP#IThe RSP# (Response Parity) signal is driven by the response agentTDIIThe TDI (Test Data In) signal transfers serial test data to the
GTL+(the agent responsible for completion of the current transaction) 1.5Vprocessor. TDI provides the serial input needed for JTAG support.
during assertion of RS[2:0]#. RSP# provides parity protection forTolerant
RS[2:0]#. RSP# should be connected to the appropriate pins/balls onTDOOThe TDO (Test Data Out) signal transfers serial test data from the
both agents on the system bus.1.5Vprocessor. TDO provides the serial output needed for JTAG support.
A correct parity signal is high if an even number of covered signalsTolerant
are low, and it is low if an odd number of covered signals are low.Open-
During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also highdrain
since it is not driven by any agent guaranteeing correct parity.TESTHIIThe TESTHI (Test input High) is used during processor test and
RSVDTBD The RSVD (Reserved) signal is currently unimplemented but is 1.5Vneeds to be pulled high during normal operation.
reserved for future use. Leave this signal unconnected. IntelTolerant
recommends that a routing channel for this signal be allocated.TESTLO[2:1]IThe TESTLO[2:1] (Test input Low) signals are used during processor
RTTIMPEDPAnalog The RTTIMPEDP (RTT Impedance/PMOS) signal is used to 1.5Vtest and needs to be pulled to ground during normal operation.
configure the on-die GTL+ termination. Connect the RTTIMPEDPTolerant
signal to VSS with a 56.2-e, 1% resistor.TESTPAnalog The TESTP (Test Point) signals are connected to Vcc and Vss at
SLP#IThe SLP# (Sleep) signal, when asserted in the Stop Grant state,opposite ends of the die. These signals can be used to monitor the Vcc
1.5Vcauses the processor to enter the Sleep state. During the Sleep state,level on the die. Route the TESTP signals to test points or leave them
Tolerantthe processor stops providing internal clock signals to all units,unconnected. Do not short the TESTP signals together.
leaving only the Phase-Locked Loop (PLL) still running. TheTHERMDA,Analog The THERMDA (Thermal Diode Anode) and THERMDC (Thermal
processor will not recognize snoop and interrupts in the Sleep state.THERMDCDiode Cathode) signals connect to the anode and cathode of the on-
The processor will only recognize changes in the SLP#, STPCLK#die thermal diode.
and RESET# signals while in the Sleep state. If SLP# is deasserted,TMSIThe TMS (Test Mode Select) signal is a JTAG support signal used by
the processor exits Sleep state and returns to the Stop Grant state in 1.5Vdebug tools.
which it restarts its internal clock to the bus andTolerant
APIC processor units.TRDY#IThe TRDY# (Target Ready) signal is asserted by the target to indicate
SMI#IThe SMI# (System Management Interrupt) is asserted asynchronouslyGTL+that the target is ready to receive write or implicit write-back data
1.5Vby system logic. On accepting a System Management Interrupt, thetransfer. TRDY# must be connected to the appropriate pins/balls on
Tolerantprocessor saves the current state and enters System Managementboth agents on the system bus.
Mode (SMM). An SMI Acknowledge transaction is issued, and theTRST#IThe TRST# (Test Reset) signal resets the Test Access Port (TAP)
processor begins program execution from the SMM handler. 1.5Vlogic. The mobile Pentium III processors do not self-reset during
STPCLK#IThe STPCLK# (Stop Clock) signal, when asserted, causes theTolerantpower on; therefore, it is necessary to drive this signal low during
1.5Vprocessor to enter a low-power Stop Grant state. The processor issuespower-on reset.
Toleranta Stop Grant Acknowledge special transaction and stops providing
internal clock signals to all units except the bus and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in the Stop Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no affect on the bus clock.
TCKIThe TCK (Test Clock) signal provides the clock input for the test bus
1.5V(also known as the test access port).
Tolerant
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