DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-24
IC2001: M65776AFP (DVDM ASSY:IC751)-2
No.Pin NameDir.Pin Functions
201-208BD[7:0]INBit stream data entry pin
2BCLKINStrobe signal of BD pin (clock)
This order effective / invalidity of data done a sample of by BD pin.
3BDENIN
It is done a sample with a start edge of BCLK.
4BDREQOUTData demand signal
5BSECHINThis order it whether data of BD pin are with top byte of a sector.
84-87
90-95MD[15:0]I/OData transfer line with SDRAM
97102
53-55
58-63MA[11:0]OUTAddress line of SDRAM
65,67,69
66,68MBA[1:0]OUTSDRAM bank choice line
70DCS
73DCS2
74DCS3OUTChip select of SDRAM
75DCS4
76DCS5
77RASOUTRAS (Row Address Strobe) control line of SDRAM
78CASOUTCAS (Column Address Strobe) control line of SDRAM
82DQMUOUTDQM control line of SDRAM
83DQMLOUTDQM control line of SDRAM
80DWEOUTWE control line of SDRAM
79MCLKOUTMovement clock of SDRAM
183PXCLKOUT27MHz pixel clock
182PXCLKPOUT54MHz pixel clock
157,158,Digital pixel data.
184-186PD[7:0]OUT
188-192Y/Cb/Cr is done multiple of by 8 bit bus, and it is output.
178CSYNCINComposite SYNC signal input terminal
179OSDKEYOUTOSD key flag output
177PWDOUTThe phase comparator output for external synchronization movement
181HSYNCOUTHorizontal synchronizing signal output pin
180VSYNCOUTVertical synchronizing signal output pin
164AO0OUTSerial PCM data for DAC
It output Lf/Rf data.
166AO1OUTSerial PCM data for DAC
It output C/Sw data.
167AO2OUTSerial PCM data for DAC
It output Ls/Rs data.
168AODOUTSerial PCM data for DAC
It is for the down mixture output.
169AADOUTAnciallary data output
176DOCLKOUTPCM bit clock
159LRCLKOUTClock for channel distinction of pulse code modulation audio system data(L/R)
173DACCLKOUTExaggerated sample movement clock of DAC
161CDBCKINThe pulse code modulation bit clock which is input by CDDSP
160CDLRCKINThe L/R clock which is input by CDDSP |
ACEC
ONKYO
