trailing edge of the Hsync input. The logic sense of this pin is controlled by Clamp
Polarity register 0FH, Bit 6. When not used, this pin must be grounded and Clamp
Function programmed to 0.
COAST Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing
with Hsync and continue producing a clock at its current frequency and phase.
This is useful when processing signals from sources that fail to produce horizontal
sync pulses during the vertical interval. The COAST signal is generally not
required for PC-generated signals. The logic sense of this pin is controlled by
Coast Polarity (register 0FH, Bit 3). When not used, this pin may be grounded and
Coast Polarity programmed to 1, or tied HIGH (to VD through a 10 k resistor) and
Coast Polarity programmed to 0. Coast Polarity defaults to 1 at power-up.
REF BYPASS Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to
ground through a 0.1 ?F capacitor. The absolute accuracy of this reference is
?4%, and the temperature coefficient is ?50 ppm, which is adequate for most
AD9883A applications. If higher accuracy is required, an external reference may
be employed instead.
MIDSCV Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to
ground through a 0.1 ?F capacitor. The exact voltage varies with the gain setting
of the Blue channel.
FILT External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter.
Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize
noise and parasitics on this node.
POWER SUPPLY
VD Main Power Supply
These pins supply power to the main elements of the circuit. They should be
filtered and as quiet as possible.
VDD Digital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz)
generates a lot of power supply transients (noise). These supply pins are identified
separately from the VD pins so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9883A is interfacing with
lower voltage logic, V DD may be connected to a lower supply voltage (as low as
2.5 V) for compatibility.
PVD Clock Generator Power Supply
The most sensitive portion of the AD9883A is the clock generation circuitry. These
pins provide power to the clock PLL and help the user design for optimal
performance. The designer should provide quiet, noise-free power to these pins.
GND Ground
The ground return for all circuitry on-chip. It is recommended that the AD9883A be
assembled on a single solid ground plane, with careful attention given to ground
current paths.
9.16. SAA7118E
9.16.1. General Description
The SAA7118E is a video capture device for applications at the image port of VGA controllers. Philips
X-VIP is a new multistandard comb filter video decoder chip with additional component processing,
providing high quality, optionally scaled, video.
The SAA7118E is a combination of a four-channel analog pre-processing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit
(CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation
by an adaptive comb filter and a high performance scalar, including variable horizontal and vertical up
and downscaling and a brightness, contrast and saturation control circuit.
19
Plasma TV Service Manual 11/01/2005 |
ACEC
HITACHI
