Pin No.Pin NameI/ODescription
This terminal is used for the two signals of the composite blanking signal (CBLNK)
and the fsc signal. Use of this terminal is determined by the register setting. When
set to CBLNK, this terminal is used as output terminal when the internal sync
95CBLNK/FSCI/O
generator is used, and is used as input terminal when the internal sync generator is not
used. When set to fsc, the signal that is obtained by dividing-frequency of XTL0 is
output. The dividing ratio of either 1/8 or 1/16 can be selected.
Composite sync signal terminal. The composite sync signal is generated by frequency-
96CSYNCO
dividing the DCLK signal. This terminal cannot accept any inputs.
ISync signal generator reset signal input. The internal generator is initialized by setting
97XSGRST
this terminal to OL�.
The clock signal that is obtained by frequency-dividing XTL0 is output from this
98CLK0OO
terminal. Dividing ratio of either 1, 1/2, 1/4 or 1/8 can be selected.
99DOUTOAudio digital output terminal.
100DATOOAudio serial data output terminal to DAC.
101LRCOOL/R clock output terminal to DAC.
102BCKOOBit clock output terminal to DAC.
Clock input for audio interface. Input the 256fs (11.2896 MHz), 384fs (16.9344
103FSXII
MHz), 512fs (22.5792 MHz) or (33.8688 MHz) etc., to this terminal.
104VDDNPower supply.
105VSSNGND.
Master clock terminal of the CD-ROM decoder and audio decoder. Either input the
clock signal to XTL2I or connect an external oscillator between XTL2I and XTL2O.
106, 107XTL2O, XTL2IO/I
Recommended frequency is 45 MHz. This clock serves for internal circuit only, and is
not synchronized with the input and output signals.
108VDDNPower supply.
This is the terminal to input the C2 pointer from CD-DSP. It indicates that the DATI
109C2POI
input has an error.
This is the terminal to input the LR clock from CD-DSP. It indicates if it is L channel
110LRCII
or R channel.
111DATIIThis is the terminal to input the serial data from CD-DSP..
This is the terminal to input the bit clock from CD-DSP. This is the clock to strobe the
112BCKII
DATI input.
113DOINIThis is the terminal to input the digital data from CD-DSP.
114XHCSIThis is the terminal of the chip select input signal during register access.
This is the terminal to output the wait signal during register access. This terminal
outputs the unique wait signal that is generated or not generated by the register, during
115XHDTI/ODRAM access when the host interface is in the parallel mode. The pull up resistor is
required since this terminal operates in the open drain configuration. Use the pull up
resistor in the serial mode operation too.
____
This terminal receives the R/W input signal when the host interface is in the parallel
116HRWI
mode. This terminal receives the serial clock input during the serial mode.
31 |
ACEC
AIWA
