IC, RL5C293
Pin No.Pin NameI/ODescription
Charge pump output/VCO input terminal (Connect an external capacitor for loop filter,
1VCOINI/Oto this terminal).
2, 19, 39, 59GNDNDigital ground.
Video mode selection control terminal (LVTTL level). NTSC mode when
3PALMODEIPALMODE = 0. PAL mode when PALMODE = 1.
Video sync mode selection control terminal (LVTTL level). Internal sync mode when
MASTERB = 0. External sync mode when MASTERB = 1. However, when
CDGMODE = 1, mode is fixed to the external sync mode regardless of MASTERB
4MASTERBIstatus so that the MASTERB terminal functions the switch selecting either 262
(NTSC) or 312 (PAL) scanning line when MASTER B = 1, or 263 (NTSC or 313
(PAL) scanning line when MASTER B = 0, in the non-interlaced scanning. (See page
10) (This terminal has the pull-up function).
5RESETBIReset input terminal (LVTTL level). Enter the reset state when this terminal is set to
OL�.
The data B input terminal (LVTTL level). Data input range is from 16 to 235, or from
6-13B7-B0I0 to 255 (as controlled by the DICNT terminal) When FORM = 0, connect this
terminal to ground.
Test input terminal Enters the test mode when TESTI0 = 1. Connect this terminal to
14TESTI0Iground or set it open.
Pixel clock input terminal (LVTTL level). When inputting the pixel clock, select the
input pixel clock frequency that is appropriate for the respective modes. (See page 7.)
15PXCLKIFrequency accuracy of the subcarrier signal of the video signal depends on that of this
clock signal. Therefore, determine the frequency accuracy of the pixel clock according
to the required accuracy of the subcarrier signal.
16, 30, 63VCCNDigital block power supply (+3.3 V or +5 V).
Horizontal sync signal input/output terminal (LVTTL level). This terminal functions
as the input terminal during the external sync mode, and as the output terminal during
17HSYNCBI/Othe internal sync mode. During the external sync mode, the input sync signal is
sampled by PXCLK and only the fall-down edge is detected. The standard cycle of
HSYNCB is 858 clock (VCD_NTSC) or 864 clock (VCD_PAL). (For CDG mode, see
page 9.) This terminal functions as the output terminal during the internal sync mode.
Vertical sync signal input/output terminal (LVTTL level). This terminal functions as
the input terminal during the external sync mode, and as the output terminal during the
internal sync mode. During the external sync mode, the input sync signal is sampled
18VSYNCBI/Oby PXCLK and the fall-down edge is detected. When the fall-down edges of
HSYNCB and VSYNCB agree, the timing is judged to be the start of the ODD field.
When they do not agree, the timing is judged to be the start of the EVEN field. This
terminal functions as the output terminal during the internal sync mode.
Input format selection terminal (LVTTL level). When FORM = 0, the input format is
20FORMICCIR-601YCbCr (4 : 2 : 2) . When FORM = 1, the input format is RGB input. (This
terminal has the pull-up function).
35 |
ACEC
AIWA
