CircuitDescription-7D15
megahertz Voltage Controlled Oscillator (VCO) andGATE
decade counter provides the 10 ns and 100 ns Clock
signal.The Voltage Controlled Oscillatorisstabilizedwith
For simplicity,the Gate block is discussed in each
a phase-locked loop circuit,in which the 100 megahertz
main
mode of operation.A block diagram, showing the
output is divided by 100 and compared with the One
signal flow, isgiven for each mode .
Megahertz Standard .The frequency differencefrom the
Phase Detector isa do errorvoltage and ispresented tothe
Voltage Controlled Oscillatorto correct any drift.
FREQUENCYMODE
Refer to Fig.3-1 for signalflow.The frequency to be
measured is connected to the B input through the B
Frequency
After amplificationand levelselection,the signals arecircuitry; then to the main gate. The 10 ms
circuitto the
shaped in the A and B Shapers . The signals are thenStandard isconnected through the A Arm
.The 10 ms
connected to the A Arm and B Arm circuitry(byway oftheGate Generator and the Arm Gate Generator
Slope circuits).This circuitrycan, with the proper com-pulse sets the Arm Gate Generator and the Gate
mand, inhibitthe signalfrom any furthertravel.A LO orGenerator HI.This enables the AND gate and opens the
ground connection tothe A ARM connector willinhibittheMain Gate .Opening the Main Gate allows the B signalto
Arm Gate
B signalwhile a HI commandatthe B ARM connectorwillbe counted . The next 10 ms pulse sets the
inhibitthe A signal. These signals,ifnot inhibited,areGenerator LO, which causes the AND Gate to go LO,
connected to the gating circuitry.turning the Main Gate off.A LO atthe output atthe AND
eseeeeChannel B SignalAveraging SignalPath
010msClockorReferenceSignal
GgrE
1433-1
Fig.3-1.Signal flow for FREC! and Frequency Ratio modes .
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