AVD-C70ES
Y DVD BOARD IC801 CXD2752R (DSD DECODER)
Pin No.Pin NameI/OPin Description
1VSCA0NGround terminal (for core)
2XMSLATISerial data latch pulse signal input from the mechanism controller
3M SCKISerial data transfer clock signal input from the mechanism controller
4MSDATIISerial data input from the mechanism controller
5VDCA0NPower supply terminal (+2.5 V) (for core)
6MSDATOOSerial data output to the mechanism controller
7M SREADYOReady signal output to the mechanism controller OL�: ready
8XMSDOEOSerial data output enable signal output terminal Not used. (Open)
9XRSTIReset signal input from the mechanism controller OL�: reset
10SMUTEISoft muting on/off control signal input from the mechanism controller OH�: muting on
11MCKIIMaster clock signal (33.8688 Mhz) input
12VSIOA0NGround terminal (for I/O)
13EXCKO1OMaster clock signal (33.8688 MHz) output to the digital audio processor
14EXCKO2OExternal clock 2 signal output terminal Not used. (Open)
15LRCKOL/R sampling clock signal (44.1 kHz) output terminal Not used. (Open)
16F75HZONot used. (Open)
17VDIOA0NPower supply terminal (+3.3 V) (for I/O)
18 to 25MNT0 to MNT7OMonitor signal output terminal Not used. (Open)
26TCKIClock signal input from the DVD system processor
27TDIISerial data input from the DVD system processor
28VSCA1NGround terminal (for core)
29TDOOSerial data output to the DVD system processor
30TMSIMS signal input from the DVD system processor
31TRSTIReset signal input from the DVD system processor OL�: reset
32 to 34TEST1 to TEST3IInput terminal for the test (normally: fixed at OL�)
35VDCA1NPower supply terminal (+2.5 V) (for core)
36UBITONot used. (Open)
37XBITONot used. (Open)
38 to 41SUPDT0 to SUPDT3OSupplementary data output terminal Not used. (Open)
42VSIOA1NGround terminal (for I/O)
43, 44SUPDT4, SUPDT5OSupplementary data output terminal Not used. (Open)
45VDIOA1NPower supply terminal (+3.3 V) (for I/O)
46, 47SUPDT6, SUPDT7OSupplementary data output terminal Not used. (Open)
48SUPENOSupplementary data enable signal output terminal Not used. (Open)
49VSCA2NGround terminal (for core)
50NCONot used. (Open)
51, 52TEST4, TEST5IInput terminal for the test (normally: fixed at OL�)
53NCONot used. (Open)
54VDCA2NPower supply terminal (+2.5 V) (for core)
55, 56NCONot used. (Open)
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for
57BCKASLI
DSD data output OL�: input (slave), OH�: output (master) Fixed at OH� in this set.
58VSDSD0NGround terminal (for DSD data output)
59BCKAIIBit clock signal (2.8224 MHz) input terminal for DSD data output Not used. (Open)
60BCKAOOBit clock signal (2.8224 MHz) output terminal for DSD data output Not used. (Open)
34 |
ACEC
SONY
