AVD-C70ES
Pin No.Pin NameI/OPin Description
46VDDENPower supply terminal (+3.3 V)
47WMD1IS-RAM wait mode setting terminal Fixed at OH� in this set
48VSSNGround terminal
49WMD0IS-RAM wait mode setting terminal Fixed at OL� in this set
50PAGE2OPage selection signal output terminal Not used. (Open)
51VSSNGround terminal
52, 53PAGE1, PAGE0OPage selection signal output terminal Not used. (Open)
54BOOTIBoot mode control signal input terminal Not used. (Fixed at OL� in this set.)
55BTACTOBoot mode state display signal output terminal Not used. (Open)
56BSTIBoot trap signal input from the system controller
PLL input frequency selection signal input terminal
57MOD1I
OL�: 384fs, OH�: 256fs (fixed at OH� in this set)
Mode setting terminal
58MOD0I
OL�: single chip mode, OH�: use prohibition (fixed at OL� in this set)
59EXLOCKIPLL lock error and data error flag input from the digital audio interface IC
60VDDINPower supply terminal (+2.6 V)
61VSSNGround terminal
62, 63A17, A16OAddress signal output terminal Not used. (Open)
64 to 66A15 to A13OAddress signal output to the S-RAM
67GP10OL/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
68GP9ODecode signal output to the system controller
69GP8IBit 1 input terminal of channel status from the digital audio interface IC
70VDDINPower supply terminal (+2.6 V)
71VSSNGround terminal
72 to 75D15 to D12I/OTwo-way data bus with the S-RAM
76VDDENPower supply terminal (+3.3 V)
77 to 80D11 to D8I/OTwo-way data bus with the S-RAM
81VSSNGround terminal
82 to 85A9, A12 to A10OAddress signal output to the S-RAM
86TDOOSimple emulation data output terminal Not used. (Open)
87TMSISimple emulation data input start/end detection signal input terminal Not used. (Open)
88XTRSTISimple emulation asychronous break input terminal Not used. (Open)
89TCKISimple emulation clock signal input terminal Not used. (Open)
90TDIISimple emulation data input terminal Not used. (Open)
91VSSNGround terminal
92 to 97A8 to A3OAddress signal output to the S-RAM
98, 99D7, D6I/OTwo-way data bus with the S-RAM
100VDDINPower supply terminal (+2.6 V)
101VSSNGround terminal
102 to 105D5 to D2I/OTwo-way data bus with the S-RAM
106VDDENPower supply terminal (+3.3 V)
107, 108D1, D0I/OTwo-way data bus with the S-RAM
109, 110A2, A1OAddress signal output to the S-RAM
111VSSNGround terminal
112A0OAddress signal output to the S-RAM
113PMIPLL reset signal input from the system controller OL�: reset
114SDI3IRear L-ch and R-ch audio serial data input from the digital audio processor
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