6. HORIZONTAL OUTPUTPin25: Black
A horizontal oscillation signal is output from pin37 ofPin26: IREF
IC201 and switches the drive transistor Q431. ThisPin27: Odd/Even output
switching signal is current amplified by the drivePin28: GND
transformer T431 and drives the output transistor Q432.Pin29: -
When Q432 becomes ON, an amplifying current flowsPin30:V-deflection stop output
directly to DY through C441 Ţ DY Ţ 0432 Ţ GND, andPin31:RGB REF
defection is performed in the last half of the scanningPin32:Blue output for OSD
period. Next, when Q432 becomes OFF, the charge thatPin33: Green output for OSD
had been stored in DY up to that point releases aPin34: Red output for OSD
resonance current to the resonant capacitors C421/C423Pin35:Blanking output for OSD
and charges them. The current stored in C421/C423 isPin36: H-sync. input (Horizontal pulse for OSD)
then flowed back to DY, and an opposite charge is thenPin37: V-sync. input (Vertical pulse for OSD)
stored in DY. This opposite charge then switches thePin38~39:Supply (+5V)
dumper diode in Q432 ON, the resonance state isPin 40: OSC GND
completed, and an amplifying current is then flowedPin 41: Oscillator input for CPU
again directly to DY through the dumper diode. By thisPin 42:Oscillator output for CPU
means, deflection in the first half of the scanning periodPin 43:Reset input
is performed, and when Q432 becomes ON at the end ofPin 44: Supply (+5V)
the first half of the scanning period, deflection during thePin 45: Protect signal input (L:Power circuit defects)
last half is begun, thus completing one cycle.Pin 46:Ident. signal input
Pin 47:R/C signal input
In the PCC circuit consisting of Q461 and Q462, thePin 48: Mute output in no picture
parabola signal supplied from the vertical circuit is addedPin 49:I2C bus SCL (Serial clock)
at the horizontal output stage and pincushionPin 50: I2C bus SDA (Serial date)
compensation is performed by varying the DC voltagePin 51:Option SW5 & Band select output1
bias. Further, the ABL voltage is feedback to the base ofPin 52:Band select output2
Q462 to compensate for width variations due to
variations in the beam current.
7. CPU <System and Teletext Control>
Pin description
Pin1: Tuning voltage output
Pin2: Brightness control output (6-bit DAC)
Pin3: Contrast control output (6-bit DAC)
Pin4: Colour control output (6-bit DAC)
Pin5: Sharpness control output(6-bit DAC)
Pin6: Not used (GND)
Pin7: Not used (GND)
Pin8: Power ON/OFF output (H:ON)
Pin9: AFT signal input
Pin10:Option SW1 & Keyboard scan input (DC)
Pin11: Option SW2
Pin12: 50/60Hz switch input (50Hz: Hi)
Pin13: GND
Pin14:TV/AV switch output (TV: Hi)
Pin15:S-VHS switch output (S-VHS: Hi)
Pin16:Option SW3 (2AV: Hi)
Pin17: Function signal input for SCART1
Pin18:Function signal input for SCART2
Pin19: Power LED drive output1
Pin20:Option SW4 & Power LED drive output2
Pin21: Ignore output
Pin22:GND
Pin23:CVBS input0 (Internal)
Pin24:CVBS input1 (Internal/External)
-5-
F2VAM |
ACEC
SANYO
