CDC-3.4
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q501 : LC78683E MP3 DECODER FOR CD
Continued from preceding page.
Pin No. Pin Name I/O Block Function
51 DVDD4 Digital I/O system power supply
Power supply
52 VSS Ground
53 MADRS7 O DRAM address output 7
54 MADRS6 O DRAM address output 6
55 MADRS5 O DRAM address output 5
56 MADRS4 O DRAM address output 4
Memory interface
57 MADRS3 O DRAM address output 3
58 MADRS2 O DRAM address output 2
59 MADRS1 O DRAM address output 1
60 MADRS0 O DRAM address output 0
61 DVDD5 Internal logic system power supply
Power supply
62 VSS GND
MP3 data request flag output (active high)
63 STREQ I/O
/DRAM data request flag input (CD-ROM mode, active high)
MP3 data transfer clock input
64 STCK I/O MP3 stream I/O
/DRAM data transfer clock output
MP3 serial data input
65 STDAT I/O
/DRAM serial data output
MP3 frame sync signal (active high)
66 FSYNC O MP3-dec
/Data continuity point detection complete flag (CD-DA mode, active high)
CRC check result output (CD-ROM data/CD-DA subcode data)
67 CRCF O CD monitor
/DRAM data output enable signal output (active high)
68 DVDD6 Digital I/O system power supply
Power supply
69 VSS GND
DRAM write enable input (CD-DA mode, active high)
70 WOK I
/DRAM data request flag input
Data continuity point detection complete flag (CD-DA mode, active high)
71 CNTOK O CD-DA shockproof
/SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output
and MP3 I/O
DRAM write interrupt flag (CD-DA mode, active high)
72 OVF O /Emphasis output flag (CD-DA and MP3 modes, active high)
/DRAM data transfer clock output
73 CMDOUT O Serial command data output (n-channel open-drain output)
74 CMDIN I Serial command data input
75 CL I Serial command clock input
Microcontroller
76 CE I Command enable input (active high)
interface
Interrupt signal output (active low)
77 INTB O
/DRAM write interrupt flag (CD-DA mode, active high)
78 RESB I System reset (active low)
79 DATAIN I Serial CD data input
CD IF
80 DATACK I CD bit clock input
Notes: 1. Notes on unused pins.
Unused input pins must be connected to the ground level (0 V).
Unused output pins must be left open. Do not connect anything to these pins.
Unused I/O pins may either be connected to the ground level (0 V) or set to output mode and left open.
2. The corresponding power supply levels must be provided to all of the DVDD1, DVDD3, DVDD4, DVDD6, and AVDD pins. The
corresponding power supply level must also be provided to DVDD2 and DVDD5. (See the Allowable Operating Ranges specifications for
the supply levels.)
3. The TEST1 and TEST2 input pins must be connected to ground (0 V).
4. The I/O pins (MDAT0:15, STREQ, STCK, and STDAT) go to input mode after a reset.
5. After first applying the power supply levels, the RESB pin must be held low for at least 1 ?s.
6. A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP.
The LC78684E does not support the implementation of an oscillator circuit using an oscillator element. |
ACEC
ONKYO
