Table 3-5-5 MD36710X (1/5)Table 3-5-5 MD36710X (2/5)
PinPin
No.NameFunctionNameFunctionNo.
Host Interface, CD-DSP interface, Sub ode interface (32 pins)35 HWIDDetermines data bus width of host
interface. It can be changed only
HD [15:12]When connecting HWID to VDD,
during reset. Host interface of
become data lines 15:12 of 16 bit host
data bus. When connecting HWID toMD36710X is set to 8 bit width at low
level (GND) and set to 16 bit width at
GND, the lines become CD-DSP serial
high level (VDD).
input port pins defined as below.
3CDERR (HD [15])CD-DSP data error input36 HORDDetermines byte order for data bus of
4CDFRM (HD [14])CD-DSP LR clock (frame) inputhost interface in 16 bit width setting.
5CDDAT (HD [13])CD-DSP data input(HWID: VDD).
6CDDAT (HD [12])CD-DSP bit clock inputIt can be changed only during reset.
HD [11:8]When connecting HWID to VDD,Set MD36710X to obtain I/O signals of
m.s. byte in HD [15:8] at low level
become data lines 11:8 of 16 bit host
(GND) and those in HD [7:0] at high
data bus. When connecting HWID tolevel.
GND, the lines become sub code port
If HWID is GND level, connect to
pins defined as below.GND.
7SCCLK (HD [11])Sub code bit clock output
9SCDAT (HD [10])Sub code bit clock input37 HTYPEDetermines protocol of host bus. It
10SCSYN (HD [9])Sub code sync signal display inputcan be changed only during reset.
11SCFRM (HD [8])Sub code frame sync inputSets MD36710X to type A at low level
and type B at High level.
12HD [7:0]8 I.s. host data bus. When connecting
14HWID to GND, only the 8 I.s. signal is130 STNDBY#Standby input (active low). All output
|defined as a host data signal. Whenpins and bidirectional pins become
16connecting HWID to VDD, 8 I.s. line isfloat state if asserting with RESET#
19used for of 16 bit data bus.and MD36710X is cut electrically from
|peripheral circuits. All internal
21operation stop and power
consumption is confined to the
22HA [3:0]Host address input. Inputs addressminimum.
24signal that specifies physical address
Contents of SDRAM are not stored at
25inside MD36710X.
26stanby.
141 RESET#Reset input (active low). Initializing
27HWR# (HR/W#)Host protocol, type A
process of MD36710X starts at the
(HTYPE=GND): HR/W#. Decidestime deasserting is carried out from
direction of host access.
assert state.
Host protocol, type B (HTYPE=VDD):
HWR#. Host writing input (active low).142 IDLEIdle, init or reset states display output
(active high).
29HCS#Host chip select input. Active low.
GPI/O signal (4 pins)
30HRD# (HDS#)Host protocol, type A (HTYPE=GND):
HDS#.2GPSIGeneral input controlled by DVP micro
Data strobe input (active low).code.
Host protocol, type B (HTYPE=VDD):
122 GPAI/O [1:0]General bidirectional pin controlled by
HRD#.
Host writing input (active low).123ADP micro code. After resetting, this
pin is defined as an input pin. ADP
31HRDYHost ready output (active high). Usecommand specifies the setting.
this signal to transmit bit stream via
159 GPSOGeneral output conrolled by DVP
host bus. External pull-up resistor is
required.micro code.
Transmission of CodBurstLen bytePLL signal (6 pins)
length is determined as 1 packet.
Check that the signal is active before126 GCLK1Master clock input for audio. Must
be connected to GCLK for usual
transmitting each packet. Possible to
write the bit stream serially up tooperation.
CodBurstLen byte to MD36710X.128 XOOutput to the crystal connected to
32HACK#Host acknowledge output (active low).GCLK. If the crystal is not used for
Protocol is type A, MD36710X assertsGCLK, XO is not connected.
this output and notify completion of129 GCLKClock for main processor or crystal
reading or writing cycle.input.
If this signal is not active, 3-state
condition occurs (External pull-up135 PLLCFG [1:0]PLL configuration input. It can be
resistor is required.).137changed only during reset. Both pins
If protocol is type B, the signalmust be connected to GND (digital)
functions as wait output signal. Whenfor usual operation.
high speed host (microprocessor) is136 PLLCACapacitor connection pin for PLL.
used, this signal may not be used.
Connect the other terminal of the
34HIRQ#Interruption requirement (active low).capacitor to PLLGND.
Deassert when host reads interruption
status resister of MD36710X. Also
deassert after host masks interruption in
the interrupt mask resister of
MD36710X or reseting.
If HIRQ# is not asserted, 3-state
condition occurs (External pull-up
resistor is required.)
3-27 |
ACEC
MITSUBISHI
