DP-IF8000
2.1.2 System Control
LRCKLchRch
BCKNote:Input a signal of some kind to DIGIT AL IN 1 and LINE IN.
LPOUT2Y MICON-DIR period
Check the DIR_XCS (IC4-37pin), SCK2 (IC4-38pin), and SDO2
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
(IC4-36pin).
32 kHz are also used.Figure 14 shows the view on the monitor after power is turned on,
Fig 9
at the instant of switching with the INPUT key.
DIR_XCS
LRCKSCK
BCK(500KHZ)
VPOUT2SDO2
Addressdata
Fig 108 bit8 bit + 8 bit
Y MAIN DSP-DIAT period00010111
Check RCS (IC12-109pin), BCK (IC12-106), VPOUT1 (IC12-Fig 14
96pin), RINFO (IC12-107pin).
Turn the power on, set in Digital Input mode, and select Y MICON-DAC periodVIRTUAL
FRONT, or VIRTUAL 5.1 or VIRTUAL 6.1 with the OUTPUTCheck the DAC_XCS (IC5-10pin), SCKO (IC5-8pin), and SDO02
switch.(IC5-9pin).
The view on the monitor when the input source sampling frequencyFigure 15 shows the view on the monitor after power is turned on,
is 48 kHz is shown in Fig. 11.at the instant of switching with the INPUT key.
The view on the monitor when the input source sampling frequency
is 44.1 kHz is shown in Fig. 12.
The view on the monitor when the input source sampling frequencyDAC_XCS
is 32 kHz is shown in Fig. 13.SCK 0
(500KHZ)
SDO 0
RCSAddressdata
BCK8 bit8 bit + 8 bit
00100000
VPOU1
RINFOFig 15
Note 4: fs=48kHz0001000 t fs=48k
Y MICON-LED DRIVER period
Fig 11Check the LED_XLAT (CN102-3pin), SCKO(CN102-6pin), and
SDO(CN102-7pin).
Figure 16 shows the view on the monitor after power is turned on,
at the instant of switching with each key.
RCS
BCK
VPOU1
RINFOLED_XLAT
SCK 0
(500KHZ)
Note 5: fs=44.1kHz0000000 t fs=44.1kSDO 0
Fig 12after data transfLAT er
8 bit + 8 bit
Fig 16
RCS
BCKY MICON-DIAT period
VPOU1Check the DIAT_LAT (IC12-152pin), SCKO (IC12-151pin), SDO
RINFO
(IC12-153pin).
Note 6: fs=32kHz0011000 t fs=32kFigure 17 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key. The timing is shown
Fig 13in detail in FIG. 18.
When OFF is selected with the OUTPUT key, check the DILRCKDIAT_LAT
(IC12-98pin), BCK (IC12-106pin), VPOUT1 (IC12-96pin), and theSCK 0
view on the monitor should be the same as the MAIN DSP-DAC
SDO 0
period.
Fig 17
DIAT_LAT
SCK 0
(500KHZ)
SDO 0
after 24bit data transfer LAT
Fig 18
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