DPR1001 harman/kardon
11. PIN DESCRIPTIONS
VD1
DGND1MCLK
AUDATA3, XMT958SCLK
WR,DS,EMWR,GPIO10LRCLK
RD,R/W,EMOE,GPIO11AUDATA0
A1, SCDINAUDATA1
A0, SCCLKAUDATA2
DATA7,EMAD7,GPIO76 5 4 3 2 1 4443424140DC
739
DATA6,EMAD6,GPIO6DD
838
DATA5,EMAD5,GPIO5937RESET
1036
DATA4,EMAD4,GPIO4AGND
1135
CS493XX-CL
VD21234VA
44-pin PLCC
1333
DGND2FILT1
14Top View32
DATA3,EMAD3,GPIO31531FILT2
DATA2,EMAD2,GPIO21630CLKSEL
1729
DATA1,EMAD1,GPIO11819202122232425262728CLKIN
DATA0,EMAD0,GPIO0CMPREQ, LRCLKN2
CSCMPCLK, SCLKN2
SCDIO, SCDOUT,PSEL,GPIO9CMPDAT, SDATAN2, RCV958
ABOOT, INTREQLRCLKN1
EXTMEM, GPIO8SCLKN1, STCCLK2
SDATAN1DGND3
VD3
VAAnalog Positive Supply: Pin 34
Analog positive supply for clock generator. Nominally +2.5 V.
AGNDAnalog Supply Ground: Pin 35
Analog ground for clock generator PLL.
VD1, VD2, VD3Digital Positive Supply: Pins 1, 12, 23
Digital positive supplies. Nominally +2.5 V.
DGND1, DGND2, DGND3Digital Supply Ground: Pins 2, 13, 24
Digital ground.
FILT1Phase-Locked Loop Filter: Pin 33
Connects to an external filter for the on-chip phase-locked loop.
FILT2Phase Locked Loop Filter: Pin 32
Connects to an external filter for the on-chip phase-locked loop.
CLKINMaster Clock Input: Pin 30
CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this input is
connected to the internal PLL from which all internal clocks are derived. When in external
clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT
118 |
ACEC
HARMAN KARDON
