DV-620H
DV-620S
Pin No.Pin nameTypeDirectionFunction
117Y/R/VOAOReset:
(DAC B)Standby: 3-S
When the Decoder outputs the composite video, this line is Y
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the Red output
118C/B/UOAOReset:
(DAC C)Standby: 3-S
When the Decoder outputs the composite video, this line is C
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the V output
115CVBS/COAOReset:
(DAC D)Standby: 3-S
When the Decoder outputs any of the types of video, this line can be programmed to output either composite or C.
120RSETIAI
Resistive load for gain adjustment of the DACs
123VREFIAI
Voltage reference for gain adjustment of the DACs
110DACDISABLEIIInput
DACs disable input. High level force the DACs to float their outputs. Low level selects normal operation of the DACs.
112COSYNC3-SO (p.d.) Reset: output (low)
Standby: 3-S
Composite sync output. Active only when RGB analog output is selected. Otherwise, the signal is low.
Digital Audio Interface (9 pins)
Pin No.Pin nameTypeDirectionFunction
144AMCLK3-SI/O (p.u.) Reset: input
Standby: 3-S
Audio Master Clock input/output. 128, 192, 256 or 384 times the sampling frequency (programmable).
146S/PDIF (AOUT4)OO (p.d.) Reset: input
Standby: 3-S
S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately can be used as a fifth audio
output. After RESET this pin outputs low level.
152AOUT[3]OO (p.d.) Reset: output (low)
151AOUT[2]Standby: 3-S
150AOUT[1]
149AOUT[0]
Serial outputs of digital stereo audio.
125AINIIInput
Serial input of digital stereo audio.
153ALRCLKOO (p.d.) Reset: output (low)
Standby: 3-S
Digital audio left/right select output for the audio port. Square wave, at the sampling frequency.
Programmable polarity interpretation for input.
154ABCLKOO (p.d.) Reset: output (low)
Standby: 3-S
Digital audio bit-clock output. Data on AOUT and AIN is output or latched, respectively, with the rising or falling
(programmable) edge of this clock.
PLL/Clock Interface (6 pins)
Pin No.Pin nameTypeDirectionFunction
132GCLKIIInput
27.000MHz clock or crystal input for main processing clock generation.
129GCLK1IIInput
27.000MHz clock input for audio master clock generation. In normal operation must be connected to GCLK.
131XOOAO
Output to a crystal that is connected to GCLK. If a crystal is not used at GCLK, XO must be left not connected.
134PLLCAAI/O
PLL Capacitor. In normal operation must be connected to a 47nF capacitor, of which the other node is connected to
GNDA.
127PLLCFG[1]IIInput
130PLLCFG[0]IIInput
PLL configuration inputs. Allowed to be changed only during RESET. In normal operation both pins must be
connected to GNDP.
30 |
ACEC
SHARP
