DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-5 Video Deinterlacer : FL12200(X35, IC700) DV-5900M only
Y Port Function
Port No.Port NameI/OFunction
Test outputs
112,113TEST(00, 01)OThese pins are test outputs and should be left unconnected in normal operation.
Test inputs
41,50,51,108These pins are used for test purposes only and should always be tied low
TEST(0~5)-
109,111for normal operation.
Power Supply Connections(Not shown on Block diagram)
1,33,63,73,84,95
Pad Ring digital power connections. Connect to the digital +3.3 volt power
105,114,123,137VDD33-
supply and decouple to the digital ground plane.
144,151, 167
2,17,34,55,64,74
85 ,96,106,115
VSS-Ground connections. Connect to the digital ground plane.
124,132, 138,145
152,159,168
43AVSS-Ground connection for the clock PLL circuits. Connect to the digital ground plane.
Core Logic digital power connections. Connect to the digital +2.5 volt
16,54,107,158AVDD25-
power supply and decouple to the digital ground plane.
Analog power connections for the clock PLL circuit. Connect to a separately
42AVDD-
decoupled +2.5 volt power supply and decouple directly to the AVSS pin.
Control Signals
Reset. When this input is set low it will reset all the internal registers
49RESETBI
to the default states.
When this pin is set high the the outputs of the FL12200 will be enabled ; when
53OEO
it is set low the outputs will be set into a high-impedance state.
56~58IFORMAT(2~0)IInput signal format control.
59~61OFORMAT(2~0)OOutput signal format control.
The settings of DADDR(1,0) allow the device address of the control bus to
44,45DADDR(1,0)-
be programmed to prevent conflict with the other devices connected to the bus.
When this pin is set low the control bus will operate in the slave mode; allowing
46MODE-
the device to programmed from an external controller.
47SDAI2-wire serial control bus data.
48SCLI/O 2-wire serial control bus clock.
40PIXCLKI Pixel clock input. This clock is used to drive all the circuits in the FL12200.
62N/P/IN/OUTI/O NTSC/PAL input or output.
Control Signals(contd.)
52NOMEMI No memory mode control input.
Input Signals
18~27G/YIN(0~9)I10-bit green or luminance signal input bus.
6~15B/CbIN(0~9)I10-bit blue or Cb chroma signal input bus.
28~32R/CrIN(0~4)
I10-bit red or Cr chroma signal input bus.
35~39R/CrIN(5~9)
3HSYNCREFIIHorizontal sync or reference.
4VSYNCREFIIVertical sync or reference.
5FIELDINIField identifier input.
Output Signals
65~72G/YOUT(2~9)
OGreen or luminance output bus.
75,76G/YOUT0,1
93,94B/CbOUT8,9
OBlue or Cb chrominance output bus.
97~104B/CbOUT(0~7)
77~83R/CrOUT(3~9)
ORed or Cr chrominance output bus.
86~88R/CrOUT(0~2)
116CCLKOOChroma output sampling clock.
117YCLKOOLuma output sampling clock.
89VREFO-Start of active field or frame indicator.
90HREFOOStart of active line indicator output.
20 |
ACEC
KENWOOD
