HITACHI DVP345E Repair Manual

SW //
PM[15] O Probe mux data output
SSCCLK // I/O // SSC clock input signal or output //
207 GPCI/O[47] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
PM[13] O Probe mux data output

PNVM/SRAM Interface (41 pins)
9,14,18,MEMDA[15-0] I/O PNVM/SRAM bidirectional data bus
22,26,30
,35,39,1
1,16,19,
24,27,33
,37,42
MEMAD[20] // O // PNVM/SRAM address bus outputs //
20 MEMCS[2]# // O // PNVM/SRAM chip select (active low) output//
GPCI/O[19] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
SW
MEMAD[19] // O // PNVM/SRAM address bus outputs //
28 PLLSEL I PLL frequency selection - 108 MHz (low) or 135 MHz (high). Level sampled
during RESET
31,34,5,MEMAD[18-14] O PNVM/SRAM address bus outputs
4,6
MEMAD[13] // O // PNVM/SRAM address bus output //
7 AFETESTEN I Audio PLL configuration input. Level sampled during RESET. In normal
operation the pin must be low during RESET
MEMAD[12] // O // PNVM/SRAM address bus output //
8 PLLCFGA I AFE test mode enable input. Level sampled during RESET. In normal operation
the pin must be low during RESET
MEMAD[11] // O // PNVM/SRAM address bus output //
10 PLLCFGP I Process PLL configuration input. Level sampled during RESET. In normal
operation the pin must be low during RESET
MEMAD[10] // O // PNVM/SRAM address bus output //
13 TESTMODE I Operational mode selection. Level sampled during RESET. In normal operation
the pin must be low during RESET.
15,17,36MEMAD[9-2] O PNVM/SRAM address bus outputs
,38,40,4
3,45,46
MEMAD[1,0] // O // PNVM/SRAM address bus output //
BOOTSEL[2,1] I CPU SW boot (and execute) source selection:
48,49 (high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART; (low, low) - Flash (low) or
Level sampled during RESET
MEMAD[0] // O // PNVM/SRAM address bus output //
49 BOOTSEL1 I CPU SW boot (and execute) source selection - Flash (low) or first debug
UART (high). Level sampled during RESET
23 MEMWR# O PNVM/SRAM write enable (active low) output.
44 MEMRD# O PNVM/SRAM read enable (active low) output.
10