DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC91 : uPD16311 FL Driver-(3)
PIN FUNCTION
Pin No.SymbolPin nameDescription
6DINData inputInputs serial data at rising edge of shift clock,
starting from lower bit.
5DOUTData outputOutputs serial data at falling edge of shift clock, starting from
lower bit. This is N-ch open-drain output pin.
9STBStrobeInitializes serial interface at rising or falling edge to make
uPD16311 waiting for reception of command. Data input
after STB has fallen is processed as command. While command
data is processed, current processing is stopped, and serial interface
is initializes. While STB is high, CLK is ignored.
8CLKClock inputReads serial data at rising edge, and outputs data at falling edge.
52OSDConnect resistor for determining oscillation frequency to this pin.
Oscillator pin
15 to 26Seg1/KS1 toSegment output pins (Dual function as key source).
High-voltage output
Seg12/KS12
(segment)
44 to 37Grid1 to Grid6Grid output pins.
High-voltage output (Grid)
27 to 32Seg13/Grid16 toTease pins are selectable for segment or grid output.
High-voltage output
35 to 36Seg20/Grid9
(segment/ grid)
50 to 46LED1 to LED6CMOS output. +20 mA max..
LED output
10 to 13Key1 to Key4Data input to these pins is latched at end of display cycle.
Key data input
1 to 4SW1 to SW4These pins constitute 4-bit general-purpose input port.
switch input
14, 33, 45VDD5 V = 10 %
Logic power
51VSSconnect this pin to GND of system.
Logic ground
34VEEVDD - 35 V max.
Pull-down level
7ICBe sure to leave this pin open (this pin is at VDD level).
Internally connection |
ACEC
ONKYO
