DescriptionGDV 100 D/002
9. Integrated Peripherals6. Front End Interface & DVD Decryption
- two UARTs to interface remote control receivers, DVD front end,The front end interface accepts sectors in the case of DVD, MPEG-1
modem �,system stream in the case of VCD and PCM data for CD-DA applications
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- one I2C controller to interface serial memories, remote controlon an IS interface. In the case of VCD and CD-DA disks the subcode
receivers, microcontrollers�,information is input via a simple asynchronous serial interface similar
- 2 SmartCard interfaces (ISO7816-3) for DVB-DSS conditionnalto a UART.
access, pay per view �,The bitstream and subcode stream then pass through a Osector
- PWM/timer module for control of system clock,processorO block which handles sector filtering in the case of DVD and
- 34 programmable I/O pins,sectorizing using the subcode stream for VCD and CD-DA systems.
- OS Link interface,The block also handles overspeed processing for all systems. The
- JTAG with boundary scan for debug.capturing of CD-DA sectors is based on a flywheel tiner to improve
robusters by concealing erros in the subcode stream. For DVD the
data, having had sector headers removed, then passes through a DVD
Y Functional Modules
conformant decryption stage and is written into any of the system
1. CPUmemories using a programmable DMA engine. When a subcode
The Central Processing Unit (CPU) on the STi5505 is the ST20-C2 32-stream is present it is locally buffered, by subcode block and can be
bit processor core. It contains instruction processing logic, instructionread by the CPU for subsequent processing, if required.
and data pointers and an operand register. It directly accesses the high
7. PWM and counter module
speed on-chip SRAM memory, which can store data or programs, and
This unit includes three separate pulse width modulator (PWM)
uses the Caches to reduce access time to off chip program and data
generators using a shared counter, and three timer compare and
memory.
capture channels sharing a second counter.
The processor can access memory via the general purpose External
The counters can be clocked from a prescaled internal clock or from a
Memory Interface (EMI) or via the SDRAM EMI which is shared with the
prescaled external clock via the capture clock input and the event on
MPEG decoder.which the timer value is captured is also programmable.
2. Memory SubsystemThe PWM counters are 8-bit with 8-bit registers to set the output high
The on-chip SRAM memory system provides 160 Mbytes/s internaltime. The capture/compare counter and the compare and capture
data bandwidth, supporting pipelined 2 cycles internal memory accessregisters are 32-bit.
at 25ns cycle times. The memory system consists of 2 Kbytes of
8. Parallel Programmable IO module
SRAM, 2Kbytes of instruction cache, a 2Kbytes data cache that can be
40 bits of parallel I/O are provided. 34 of then are connected to actual
programmed to be SRAM, and an external memory interface (EMI).
PIO pins. Each bit is programmable as an output or an input. The output
The STi5505 product has 2 Kbytes of on-chip SRAM. The advantage
can be configured as a totem pole or open drain driver. Input compare
of this is the ability to store time critical code on chip, for instance
logic is provided which can generate an interrupt on any change on any
interrupt routines, software kernels or device drivers, and even frequently
input bit.
used data without these being flushed from the caches.
Many pins of the STi5505 device are multifunction and can either be
The instruction and data caches are direct mapped with a write-back
configured as PIO or connected to an internal peripheral signal.
system for the data cache and support burst accesses to the external
memories for refill and write-back which are effective for increasing9. MPEG Video decoder
performance with page-mode and SDRAM memories.The video decoder is a real-time video compression processor
The STi5505 EMI controls access to the external memory andsupporting the MPEG-1 and MPEG-2 standards at video rates up to
peripherals while the SDRAM EMI provides access to the SDRAM720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion
buffer for the MPEG decoders, ST20 and DMA peripherals.for display is performed by vertical and horizontal filters. User-defined
The STi5505 EMI can access a 16 Mbytes (or greater if DRAM is used)bitmaps may be superimposed on the display picture through use of
physical address space in each of the four general purpose memorythe on-screen display function.
banks, and provides sustained transfer rates of up to 80 Mbytes/s.
10. PAL/NTSC encoder
Peripherals that support an asynchronous data acknowledge are
The digital encoder which is integrated in the STi5505 converts a
supported as is an external Power PC which can share the bus with the
multiplexed 4:2:2 YUV stream into a standard analog baseband PAL/
STi5505 and access the SDRAM buffer through the device.
NTSC signal and into RGB analog components. The encoder can also
High memory bandwidths up to 200 Mbytes/s can be supported by the
perform closed-caption, CGMS or teletext encoding and allows
SDRAM EMI.
Macrovision TM 7.01/6.1 copy protection.
The internal memory interconnect provides buffering and arbitration of
memory access requests to sustain very high throughput of memory11. MPEG-2 Audio / Dolby AC-3 Decoder
accesses.The audio decoder is a Dolby AC-3 decoder capable of decoding both
5.1 and 2 channel DVD comformant bitstreams. The decoder also
3. System Services Module
handles MPEG-1 (layers 1 & 2) and MPEG-2 layer 2 (6 channels).
The system services module includes :
Downmix to 2 channels is possible for Dolby and MPEG standards with
- Phase locked loop (PLL) - accepts 27MHz input and generates all
optional pro-logic encoding.
the internal high frequency clocks needed for the CPU and the OS-
The decoder directly accepts MPEG-2 PES streams as input. The
Link.
decoder is capable of supporting IEC6958-IEC61937 formatted outputs
- test access port - JTAG compatible.
for AC-3 and MPEG audio, linear PCM (left & right,16, 18, 20 & 24 bits),
- Diagnostics controller accessed via the JTAG port providing :
zero output (Mute mode) and PCM audio.
- Bootstrapping during development
- Hardware breakpoint and watchpoint
- Real time trace
- External LSA triggering support.
4. Serial Communications
To facilitate the connection of this system the front end device and
other peripherals, two UARTs (ASCs) are included in the device. The
UARTs provide an asynchronous serial interface.
The UART can be programmed to support a range of baud rates and
data formats, for example, data size, stop bits and parity. Two
synchronous serial communications (SSC) interfaces are provided on
the device. These can be used for a remote control device for example
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via an IC or SPI bus.
5. Interrupt Subsystem
The STi5505 interrupt subsystem supports eight prioritized interrupt
levels. Two external interrupt pins are provided. Level assignment
logic allows any of the internal or external interrupts to be assigned
and, if necessary, share any interrupt level.
2 - 12GRUNDIG Service |
ACEC
GRUNDIG
