Pin No.Pin NameI/ODescription
45TCKITest mode control input pin. Fix at OH�
46TDOOTest data bus pin. (Not used)
47VSSNDigital ground
The functions of this pin are selected by Pin 64 XIICEN.
48SIIWhen the XIICEN pin is OH�, sets into the SONY SIO mode, and becomes the SI serial data input pin.
When the XIICEN pin is OL�, sets into the I2C-BUS mode, and becomes the SDA input/output pin
The functions of this pin are selected by Pin 64 XIICEN.
49SCKIWhen the XIICEN pin is OH�, sets into the SONY SIO mode, and becomes the SCK serial clock input pin.
When the XIICEN pin is OL�, sets into the I2C-BUS mode, and becomes the SCL input pin
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is OH�, sets into the SONY SIO mode, and becomes the XCK chip select input pin.
50XCSI
When the XIICEN pin is OL�, sets into the I2C-BUS mode, and becomes the SA slave address selection input
signal which selects the I2C-BUS slave address
Active OL� vertical sync reset input pin. Pulled-up.
51XVRSTIUsed for synchronizing external vertical sync and internal vertical sync.
When XVRST is OL�, the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined by this signal.
52F1I
OH� indicates the first field.
OL� indicates the second field
53VDDNDigital power supply
Test mode control input pin. Pulled-up.
54XTEST4IWhen these pins are OH�, CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active OL�.
55XRSTI
During power on/reset, set to OL� for more than 40 clocks (SYSCLK)
ISystem clock input pin.
56SYSCLK
To generate the correct sub carrier frequency, precisely 27MHz is required
13.5MHz pixel data clock output pin. This clock is obtained by 1/2 frequency-dividing SYSCLK.
57PDCLKO
Used only in the 16-bit pixel data mode
58VSSNDigital ground
59VSYNCOV.sync signal output
60HSYNCOH.sync signal output
The functions of this pin are selected by Pin 64 XIICEN.
61SOOWhen the XIICEN pin is OH�, sets into the SONY SIO mode, and becomes the S0 serial-out output pin.
When the XIICEN pin is OL�, this pin is not used and sets into high impedance (Not used)
Field ID output.
62FIDOWhen control register bit OFDS�=O1�, OL� indicates the first field and OH� indicates the second field.
When control register bit OFDS�=O0�, OH� indicates the first field and OL� indicates the second field
63VDDNDigital power supply
Serial interface mode selection input pin. Pulled-up.
64XIICENIWhen OL�, Pins 48 to 50, and 61 set into the I2C-BUS mode.
When OH�, Pins 48 to 50, and 61 set into the SONY SOP mode
N 65 N |
ACEC
SONY
