Pin No.Pin NameI/ODescription
Internal trap filter control terminal (LVTTL level). Trap filter display is disabled when
21TRAPFENITRAPFEN = 0. Trap filter is enabled when TRAPFEN = 1. (This terminal has the pull-
up function).
The G data or Y data input terminal (LVTTL level). The data input range is from 16 to
22-29G7-G0I235 or from 0 to 255 in the case of the G data (as controlled by the DICNT terminal),
and the data input range is from 16 to 235 in the case of the Y data.
The R data or CbCr data input terminal (LVTTL level). The data input range is from
31-38R7-R0I16 to 235 or from 0 to 255 in the case of the R data (as controlled by the DICNT
terminal), and the data input range is from 16 to 240 in the case of the CbCr data.
40CLKOUTOClock output terminal Clock output of the doubled frequency of PXCLK when
CLKMODE = 0. Clock output of 1/2 the frequency of PXCLK when CLKMODE = 1.
Field indication signal output terminal Outputs OH� when the field is the ODD field.
41FLDOUTOOutputs OL� when the field is the EVEN field. Polarity of the terminal becomes
invalid during the external sync mode.
Clock output terminal for OSD_IC The clock signal having 1/2 the frequency of the
input PXCLK frequency is output when CLKMODE = 0. The clock signal having 1/4
42OSDCLKOthe frequency of the input PXCLK frequency is output when CLKMODE = 1. (See
page 6.)
The video data input control terminal (LVTTL level). Set this terminal to DICNT = 0
normally. When DICNT = 1 is set, the data input range of RGB can be expanded to
43DICNTIthe range of 0 to 255 on the condition that FORM = 0. When FORM = 1, the Cb data
can be input starting from the odd cycle. (See page 8.) (This terminal has the pull-up
function).
The SLEEP mode control terminal (LVTTL level). Normal operation mode is selected
44SLEEPIwhen SLEEP = 0. The SLEEP mode is selected when SLEEP = 1.
45AVCCNAnalog block power supply (+5 V).
46, 47, 50NCNBe sure to set this terminal to open.
48VIDEOOAnalog video output terminal (This terminal is driven in 37.5 W ).
49IREFNAn external resistor is connected to this terminal, that sets the full scale output current
value.
51COMPNAn external de-coupling capacitor is connected to this terminal, that is used for phase
compensation.
52, 53AGNDNAnalog ground.
CDG_PAL4FSC mode selection control terminal. (LVTTL level). Status of this
PAL4FSC terminal is made valid only when PALMODE = 1 and CDGMODE = 1.
54PAL4FSCIThe mode is the CDG_PAL908fH mode when PAL4FSC = 0. The mode is the
CDG_PAL4FSC mode when PAL4FSC = 1.
The input terminal to specify the OSD color. (LVTTL level). This input signal
sampled by PKCLK and is encoded instead of the data supplied from the RGB input
55-57OSD2-OSD0Iterminal when VSW = 1. When the OSD function is not used, connect this terminal to
ground.
36 |
ACEC
