CPU (LSI105: UPD912GF-3BA)
The 16-bit CPU contains a 1k-byte RAM, three 8-bit I/O ports, two timers, a keycontroller and serial interfaces.
The CPU detects key velocity by counting the time between first-key input signal FI and second-key SI from
the keyboard. The CPU reads sound data and velocity data from the sound source ROM in accordance with
the selected tone; the CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then the
CPU provides 16-bit serial sound data to the DSP. The CPU also controls MIDI input/output and stores
sequencer data into the working storage RAM.
The following table shows the pin functions of LSI105.
Pin No.TerminalIn/OutFunction
1TXD0Out MIDI signal input
2RXD0In MIDI signal output
3SCK0Out APO (Auto Power Off) signal output
4, 5TXD1, RXD2N Not used. Connected to ground.
6SCK1Out 1 MHZ synchronizing pulse output
7AVCCIn Ground (0 V) source
8, 9AN0, AN1N Not used. Connected to ground.
10AGNDIn Ground (0 V) source
11BCKOut Bit clock output
12SOOut Serial sound data output
13LRCKOut Word clock output
14GNDIn Ground (0 V) source
15, 16XLT0, XLT1In/Out 20 MHz clock input/output
17VCCIn +5 V source
18, 19MD0, MD1In Mode selection terminal
20RSTBIn Reset signal input
21NMIIn Power ON signal input
22INTN Not used. Connected to ground.
FI0 ~ FI3
23 ~ 30In Terminal for key input signal
SI0 ~ SI3
31 ~ 38KC0 ~ KC7Out Terminal for key scan signal
FI4 ~ FI7
39 ~ 46In Terminal for key input signal
SI4 ~ SI7
47, 48FI8, SI8In Terminal for pad input signal
49FI9In Terminal for button input signal
50SI9In Sustain signal input
51FI10In Terminal for button input signal
52SI10In Not used
53 ~ 55KI0 ~ KI2In Terminal for button input signal
56MWNBOut Write enable signal output
57 ~ 76MA0 ~ MA17Out Address bus
77MCSB0Out Chip enable signal output for the sound source ROM
78MCSB1Out Not used
79MCSB2Out Chip enable signal output for the DSP
N 6 N |
ACEC
