Gate Array (UPD65005C-578)
Functions of the gate array are;
(1) To decode chip select signals for the working strage RAM, the DSP and the key touch LSI.
(2) To hold the following signals on "Low" during power off.
Read/write enable signals for the DSP and the key touch LSI
10MHz clock for the key touch LSI
(3) To generate button scan / LED drive signals.
The following table shows the pin functions of the gate array.
Pin No. TerminalIn/OutFunction
1-RESETIn Reset signal input
2-RDAPOOut Read enable signal output
3-WRAPOOut Write enable signal output
4-LSISOut Chip select signal for the DSP
5-HGOut Chip select signal for the key touch LSI
6PHAPOOut 10MHz clock for the key touch LSI
7-SRAMOut Chip select signal for the working strage RAM
8 ~ 9KO8 ~ KO9 Not used.
10 ~ 17KO7 ~ KO0Out Button scan / LED drive signal output
18 ~ 20 Not used.
21GNDIn Ground (0V) source
22PHAIn 10MHz clock input
23-WRIn Write enable signal input
24-RDIn Read enable signal input
25-APOIn APO (Auto Power Off) signal input
26KOCIn KO signal data input
27KODIn Clock for KO signal data
28 ~ 39A15 ~ A4In Address bus
40, 41D0, D1In Data bus
42VDDIn +5V source
LSIS(Chip select sigal for the DSP)
A4 ~ A15HG (Chip select signal for the key touch LSI)
Address decoder
SRAM(Chip select signal for the working strage RAM)
D0, D1
RDAPO
RD(Read enable signal controlled by APO)
WRAPO
WRController(Write enable signal controlled by APO)
PHAPHAPO
APO(10MHz clock for the key touchLSI.
Controlled by APO)
KOD
Shift registerKO0 ~ KO7(Button scan / LED drive signal)
KOC
RESET
N 7 N |
ACEC
