IC description
1.1.9 PWM Output- Rounding, fringe, double width, double height,
Control of TV settings is able to be made with up to eight scrolling, cursor, full background colour,
8-bit PWM outputs, with a frequency maximum of semitransparent mode and reduced intensity colour
23,437Hz at 8-bit resolution(INTCLK=12 MHz). Low reso- supported
lutions with higher frequency operation can be pro-Teletext unit, including Data slicer, Acquisition Unit and
grammed.up to 8K Bytes RAM for Data Storage
1.1.10 Serial Peripheral Interface (SPI)VPS and Wode Screen Signalling slicer
The SPI bus is used to communicate with external Integrated Sync Extractor and Sync Controller
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devices via the SPI, or bus communication stan-I C14-bit Voltage Synthesis for tuning reference voltage
dards. The SPI uses one or two lines for serial data and a Up to 6 external interrupts plus 1 non-maskable inter-
synchronous clock signal.rupt
1.1.11 Standard Timer (STIM)8x8-bit programmable PWM outputs with 5V open-
The Standard Timer includes a programmable 16-bit drain or push-pull capability
down counter and an associated 8-bit prescaler with Sin-16-bit Watchdog timer with 8-bit prescale
gle and Continuous counting modes.16-bit standard timer with 8-bit prescaler usable as a
1.1.12 Analog/Digital Converter (ADC)Watchdog timer
In addition there is a 3 channel Analog to Digital Con-3-channel Analog-to-Digital converter ; 6-bit guaran-
verter with integral sample and hold, fast 5.7us conver-teed
sion timer and 6-bit guaranteed resolution.Rich instruction set and 14-Addressing modes
Versatile Development Tools, including Assembler,
(2) FeatureLinker, C-compiler, Archiver, Source Level Debugger
Register File based 8/16 bit Core Architecture with and Hardware Emulators with Real-Time Operating
RUN, WFI, SLOW and HALT modesSystem available from third parties
OO
to operating temperature range0 C70 CPiggyback board available for prototyping
Up to 24 MHz Operation @5V 10%+_
Minimum instruction cycle time : 375ns at 16MHz inter-
nal clock
64K Bytes ROM
256 Bytes RAM of Register file(accumulator or index
registers)
256 Bytes of on-chip static RAM
8K Bytes of TDSRAM(Teletext and Display RAM)
56-lead Shrink DIP package
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer and Core
clocks running from one single low frequency external
crystal.
Enhanced Display Controller with 26 rows of 40/80
characters
- Serial and Parallel attributes
- 10x10 dot Matrix, 512 ROM characters, definable by
user
- 4/3 and 16/9 supported
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ACEC
