CIRCUIT OPERATING MANUAL
(1) Structure
Block move
DMAST20
CPU
2 MPEG
DMAs
SerialInterrupt
IEEE 1394controller
SDAV
interface
EMI
Hardware
transport
strearn
demux
2
SmartCard
interfaces
2 Kbytes(ASC)
Instruction
cache
MPEG
audio
decoder
2K DataAC-3 I/F
cache and
2K SRAM
MPEG
video
decoder
OS-Link
2 UART
2
1 IC
PIO
3 PWMPAL/NTSC
Encoder
Diagnostic
controller
andTeletest
systemsinterface
services
Feature 5. Sti5500 Block Diagram
STI5500 is a 1 chip including 32bit RISC CPU, A/V Demux, Video Encoder, Multi PIO and Cache RAM for the use of
DVB and DSS Set Top.
Followings are summary of distinctive features of each Block.
Enhanced capability with 32bit VL-RISC CPU Core of 50MHZ clock.
Supporting Bandwidth of 200MB/S using internal 2KB SRAM buffer and 2KB DCACHE.
Video Decoder is attached inside supported by MPEG-2 MP@ML and Letter Box.
MPEG Layer1 and 2 Audio Decoder are stored inside.
Providing interface external AC3 Decoder.
Supporting 2 - 8bit/pixel OSD.
Internally stored Video Encoder for the output of RGB, CVBS and Y/C Video
Enhanced CPU and Decoder capability boosted by 32Mbit SDRAM.
Backing External Surrounding Interface Memories. ( 4 Banks )
Able to use Hardware DMUX, input Serial and to support 32Pid.
Boosting 8 Level INT.
Supporting DMA and other multi PID.
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ACEC
