Y Coincidence detector (Synchronization Lock SL)
The coincidence detector detects whether the incoming CVBS signal is synchronized with the horizontal oscillator,
2
thus whether the PHI-1 loop is in-lock. The output is available by IC bus, SL, and can be used for search tuning and
OSD. In automatic mode (FOA/FOB=00) the coincidence detector switches for out of lock condition the PHI-1loop to
fast to ansure fast horizontal catching. During search tuning the coincidence detector can be made less sensitive
(about 5 dB) by control bit STM(search tuning mode). This prevents false stops.
Y Vertical sync separator
The vertical sync separator separates the vertical sync pulse from the composite sync signal. This separated sync
pulse is used to trigger the vertical divider system. To generate a trigger pulse for the divider the minimum pulse
width of the incoming vertical sync pulse must be 17?s.
The integrator network is designed such that for anticopy signals (e.g. Macrovision) with vertical pulses of 10?s(0n)
and 22?s(off) still a vertical sync pulse is generated. (because more lines with vertical pulses are present, pulse
width of less than 17?s is allowed, by integration still the required level is reached).
To improve the behaviour for such anticopy signals, a special circuit has been implemented to prevent disturbance
of the PHI-1. This circuit is only active when there is coincidence (SL=1) and a Osuper norm� signal is detected
(exact 525 or 625 lines / frame)
Vertical synchronisation, normal(above) and with anticopy signal(below)
Y Vertical divider system
The divider system uses a counter that delivers the timing for the vertical ramp generator in the geometry processor.
The clock is derived from the horizontal line oscillator.
The divider system synchronizes on the vertical sync pulse of the vertical sync separator.
For the TDA8846/47/57 only the 60Hz figures are valid.
The divider has three modes of operation :
1. Search mode(large window)
This mode is activated when the circuit is not synchronized or when a non-standard signal is received. In the
search mode the divider can catch between about 45 and 64.5Hz. For the TDA8846/47/57 these figures are about
54 to 64.5Hz)
Only in RGB input mode, the catching range is enlarged and ranges from 45 to 72 Hz. (54 to 72 for TDA
8846/47/57). With this range it is possible to display converted Personal Computer signals on an adapted TV-
receiver.
2. Standard mode (narrow window)
This mode is switched on (coming from search mode) when more than 15 successive vertical sync pulses are
detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the
retrace of the vertical ramp generator is started at the end of the window (thus automatic insertion of missing verti-
cal sync pulses). As consequence the disturbance of the picture is very small. The circuit will switch back to the
search window when 6 succeeding vertical periods no sync pulses are found within the window. In the narrow win-
dow mode the PHI-1 is inhibited during the verical eqalization pulses to prevent disturbance.
36 |
ACEC
