APPENDIX
IC DESCRIPTION
(4) PIN DESCRIPTION
RESET Reset (input, active low). The ST9+ is initialised HYNC/CSYNC Horizontal/Composite sync. Horizontal
by the Reset signal. With the deactivation of RESET, or composite video synchronisation input to OSD. Posi-
program execution begins from the Program memory tive or negativety.
location pointed to by the vector contained in program PXFM Analog pin for the Display Pixel Frequency Multi-
memory locations 00h and 01h.plier
R/G/B Red/Green/Blue. Video color analog DAC out-AVDD Analog VDD of PLL. This pin must be tied to
putsVDD externally to the ST92195.
FB Fast Blanking. Video analog DAC output.GND Digital circuit ground.
VOD Main power supply voltage(5V 10%, digital)AGND Analog circuit ground(must be tied externally to
WSCF, WSCR Analog pins for the VPS/WPP slicer line digital GND).
PLL.CVBS1 Composite video input signal for the Teletext
MCFM Analog pin for the display pixel frequency multi-slicer and sync extraction.
plier.CVBS2 Composite video input signal for the VPS/WSS
OSCIN, OSCOUT Oscillator (input and output).slicer. Pin AC coupled.
These pins connect a parallel-resonant crystal(24MHz AVDD1, AVDD2 Analog power supplies(must be tied
maximum), or an external source to the on-chip clock externally to AVDD).
oscillator and buffer. OSCIN is the input of the oscilltor TXCF Analog pin for the VPS/WSS line PLL.
inverter and internal clock generator; OSCOUT is the CVBSO, JTDO, JTCK Test pins : leave floating.
output of the oscillator inverter.JTMS, TEST0 Test pins : must be tied to AVDD2.
VSYNC Vertical Sync. Vertical video synchronisation JTRST0 Test pin : must be tied to GND.
input to OSD. Positive or negative polarity.
Figure 2. Pin Description
4 |
ACEC
