CIRCUIT OPERATIONAL DESCRIPTION
4) SDRAM : HY57V161610ET-7 (DV-1000S/DV-1100S/DV-1200S/DV-1300S/DV-1400S/DV-710S)
This sends and receives data with MPEG decoder and performs the video signal processing.
Every video signal output from DVD player is once stored in SDRAM and then encoded in
MPEG decoder and nally output into the analog signal.
SDRAM applied to DVD module has the capacity of 16MBit(1048576 x 16bit x 1Bank), sends
and receives data with MPEG decoder by 16 bit.
Description
THE Hynix HY57V161610E is a 16,777,216 bits CMOS Synchronous DRAM, ideally
suited for the main memory and graphic appli-cations which require large memory den-
sity and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.
HY57V161610E is offering fully synchronous operation referenced to a positive edge
clock. All inputs and outputs are synchronizedwith the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth. All input and
outputvoltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the
number of consecutive read or write cycles initi-ated by a single control command (Burst
length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
Aburst of read or write cycles in progress can be terminated by a burst terminate com-
mand or can be interrupted and replaced by anew burst read or write command on any
cycle. (This pipeline design is not restricted by a `2N` rule.)
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ACEC
