DescriptionsGDV 100 D
A/V MUX BoardDigital Board
IC7503 TDA1305T: Bitstream continuous calibration DAC IC7100 DRC: DRAM Controller
Function OverviewFunction Overview
The TDA1305T is a dual CMOS DAC with upsampling filter and noiseThe DRAM-Controller (DRC) interfaces between the CPU (IC7111)
shaper. The combination of high oversampling up to 16-fold, 2nd orderand 1 or more DRAMs (IC7102,IC7103). In addition it provides 4 chip-
noise shaping and continuous calibration conversion ensures that onlyselect lines (not used). Basically, when the CPU wants to read/write
simple 1st order analog post-filtering is required.data from/into the DRAM, the DRC merely provides the DRAMs with
Two on board operational amplifiers convert the digital-to analogthe appropriate control-signals (RAS, CAS, WE, OE) and addresses,
current to an output voltage. Externally connected capacitors performwhile the databus is connected directly between the DRAMs and the
the required 1st order filtering so that no further post-filtering isCPU. To maintain the data integrity in the DRAMs, the DRC (almost)
required.periodically refreshes the DRAMs in bursts of 8 Cas-Before-Ras
cycles.
1092141572812
FILTCL237100750318345268
VDDDVSSDVDDX VSSXVSSO VDDOVDDAVSSADRC
TDA1305T
33VDD1VDD2VDD3VDD5
AI1
LEFT36-VOL22AI2
6 DATAOUTPUT37STAGE+AI3
SERIAL386AI4AO1
4 BCK3930
DATA FILTCR24AI5AO2
DAC4032AI6AO3
5 WSINPUT4131 RIGHTAI7AO4
OUTPUT467
STAGE-VOR257AI8MUXAO5 66
3TEST1+92AI9AO6
AI10AO7
1064
11TEST2AI11AO8
TIMING113
AI12AO9
12AI13
15
CKSL1CKSL2SYSCLKRESCDEC16DEEM1DEEM2MUSBDSMBATSBVREFAI14
AI15
DRAM
7812131617 18 19 20 212617AI16
20
AI17
21CONTROLLER
AI18
Pin NameI/O Function25
AI19
1VDDA-Positive supply voltage (analog part)2613CS1
AI2014
28CSCS2
2VSSA-supply ground (analog part)AI21
2958CSRM
3TEST1Itest input (connected to ground)43AI22GEN57CSTOTN
AI23
4BCKIbit clock input
65
5WSIword select inputRESETNRAS2 4846
59UCAS2
6DATAIdata inputASN4744LCAS2
UDSN5
7CKSL1Iclock selection 145HOSTDRAMWE
LDSN63
56
8CKSL2Iclock selection 2OERWN22
55I/FI/FRAS1
9VSSD-supply ground (digital part)UCAS1DTACKN23
5424
10VDDD-Positive supply voltage (digital part)LCAS1
51MODE1
11TEST2Itest input (connected to ground)50REFR62MODE2
MODE3
REFRESH
12SYSCLKIsystem clock49
CLK
13RES-not connectedVSS1 VSS2 VSS3 VSS4 VSS5 VSS6VSS7 VSS8 VSS9
14VDDX-Positive supply voltage1935536118274260
15VSSX-supply ground
16CDECO system clock outputPin nameI/OFunction
17DEEM1Ideemphasis on/offMODE[3:1]IMode inputs
18DEEM2Ideemphasis on/offCLKIClock
19MUSBImuting (active low)AI[23:1]IAddress input:
20DSMBIdouble speed modeAI23-AI19: bank of 512 Kbytes
21ATSBI12 dB attenuationAI18-AI10: column address
22VOLO left channel outputAI10-AI01: row address
23FILTCLIcapacitor for left channel 1st order filterASNIAddress strobe
24FILTCRIcapacitor for right channel 1st order filterUDSNIUpper Data strobe
25VORO right channel outputLDSNILower Data strobe
26VREFO internal reference voltage for output channels (VDD/2) RWNIRead/write
27VSSO-supply ground (operational amplifier)RESETNIReset
28VDDO-positive supply voltage (operational amplifier)AO[9:1]IAddress output
RAS1, RAS2ORow Address strobe
UCAS1, UCAS2OUpper column address strobe
LCAS1, LCAS2OLower column address strobe
WEOWrite enable
OEOOutput enable
DTACKNOData acknowledge
REFRORefresh
CS1NOChip select 1
CS2NOChip select 2
CSROMNOChip select ROM
CSTNOChip select total
GND�Ground
VCC�Power supply
k 2 - 14GRUNDIG Service |
ACEC
