HITACHI DVP345UK Repair Manual

RFDAT[4] O RF channel sample data inputs for AFE by-pass
ICGPCI/O[7] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
203 to the CPU //
DVDERR // I // DVD-DSP error input for FE by-pass. Programmable polarity//
RFCLK // O // RF channel sampling clock output for AFE by-pass //
PM[12] O Probe mux data output
DEFECT // I/O // Disc defect input or output signal //
IDGPCI/O[5] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
200 SW. When input, the pin can be used as general purpose external interrupt
to the DSP //
DVDSTRB // O // AV data bit strobe (clock) input for FE by-pass. Programmable polarity //
RFDAT[5] I RF channel sample data inputs for AFE by-pass
ICGPCI/O[6] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
201 to the CPU //
DVDVALID // I // AV data valid input for FE by-pass. Programmable polarity //
PM[16] O Probe mux data output

SDRAM Interface (36 pins)
103,100,RAMDAT[15-0] I/O SDRAM bidirectional data bus
98,94,90
,88,85,8
2,84,86,
89,92,96
,99,102,
104
69,65,67RAMADD[11-0] O SDRAM address bus output
,63,60,5
7,55,53,
54,56,59
,61
74 RAMRAS# O SDRAM row select (active low) output
75 RAMCAS# O SDRAM column select (active low) output
80 PCLK O SDRAM clock output (same as internal processing clock).
78 RAMDQM O SDRAM data masking (active high) output
71 RAMBA[0] O SDRAM bank select output
70 RAMCS[0]# // O SDRAM chip select (active low) //
RAMBA[1] SDRAM bank select output
73 RAMCS[1]# O SDRAM chip select (active low) output
77 RAMWE# O SDRAM write enable (active low) output.

SSC Interface (3 pins)
SSCTXD // O // SSC data output signal //
208 GPCI/O[16] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
PM[14] O Probe mux data output
SSCRXD // I // SSC data input. //
1 GPCI/O[17] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
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