OC440LX Motherboard Technical Product Specification
2.5 Interrupts
Table 36. Interrupts
IRQSystem Resource
NMII/O channel check
0Reserved, interval timer
1Reserved, keyboard controller
2Reserved, cascade interrupt from slave PIC
3COM2*
4COM1*
5LPT2 (Plug and Play option)/audio/user available
6Diskette drive controller
7LPT1*
8Real time clock
9Reserved
10USB/user available
11Windows Sound System* / user available
12PS/2 mouse port (if present, else user available)
13Reserved, numeric processor
14Primary IDE (if present, else user available)
15Secondary IDE (if present, else user available)
* Default, but can be changed to another IRQ
2.6 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI expansion slots and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in board.
PCI devices are categorized as follows to specify their interrupt grouping:
? INTA: By default, all add-in boards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
? INTB: Generally, the second interrupt on add-in boards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
? INTC and INTD: Generally, a third interrupt on add-in boards is classified as INTC and a
fourth interrupt is classified as INTD.
52 |
ACEC
