DV-505/DVF-4050/-S
CIRCUIT DESCRIPTION
Block Diagram for D/A Converter
BCKSerial
LRCKInput
DATAI/FOutput Amp andVout L
DACLow-pass Filter
8X
OversamplingEnhanced
Digital FilterMulti-level
withDelta-Sigma
MLVcom
Functionmodulator
ControllerFunction
MC
ControlDACOutput Amp and
Low-pass Filter
MDII/FVout R
System Clock
System
SCKClockZero DetectPower Supply
Manager
VDDVCC
DGNDAGND
ZERO LZERO R
64 Bit SDRAM : HY57V651620B(IC301)
Pin No.Pin NameI/ODescription
The system clock input. all other inputs are registered to the SDRAM
38CLKI
on the rising edge of CLK
Controls internal clock signal and when deactivated,the SDRAM
37CKE-
will be one of the states among power down, suspend or self refresh.
19CS-Enables or disables all inputs except CLK, CKE, and DQM.
Selects bank to be activated during RAS activity.
20,21BA0,BA1-
Selects bank to be read/written during CAS activity.
22~26Row address : RA0~RA11, Column address : CA0~CA7
A0~A11-
29~35Auto-precharge flag : A10
16,17,18WE,CAS,RAS-WE, CAS and RAS define the operation.
15,39LDQM,UDQMI/O Controls output buffers in read mode and masks input data in write mode.
2,4,5,7,8,10
11,13,42,44DQ0~DQ15I/O Multiplexed data input/output pin.
45,47,48,50
1,3,9,14,27
VCC/VCC Q-Power supply for internal circuits and input buffers.
43,49
10VSS/VSS Q-Ground terminal.
36,40NC-Unused.
Flash Memory : M29F400T-90N1(IC401)
Pin No.Pin NameI/ODescription
25,24~16,8~1A0~A18IAddress Inputs
29,31,33,35
DQ0~DQ7I/O Data Input/Outputs, Command Inputs
38,40,42,44
30,32,34,36
DQ8~DQ14I/O Data Input/Outputs
39,41,43
45DQ15I/O Data Input/Outputs or Address input
26CE-Chip Enable
28QE-Output Enable
11WE-Write Enable
12RP-Reset/Block Temporary Unprotect
15RY/BYoReady/Busy/Output
47BYTE-Byte/Word Organization
37VCC-Supply Voltage
27,46VSS-Ground
8 |
ACEC
