DV-605/DVF-R5060-S
CIRCUIT DESCRIPTION
2-3 64 Bit SDRAM : HY57V651620B (Main, IC31)
Pin No.Pin NameI/ODescription
The system clock input. all other inputs are registered to the SDRAM on
38CLKI
the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be
37CKE-
one of the states among power down, suspend or self refresh.
19CS-Enables or disables all inputs except CLK, CKE, and DQM.
Selects bank to be activated during RAS activity.
20,21BA0,BA1-
Selects bank to be read/written during CAS activity.
22~26Row address : RA0~RA11, Column address : CA0~CA7
A0~A11-
29~35Auto-precharge flag : A10
16,17,18WE,CAS,RAS-WE, CAS and RAS define the operation.
15,39LDQM,UDQMI/OControls output buffers in read mode and masks input data in write mode.
2,4,5,7,8,10,11,
13,42,44,45,47,DQ0~DQ15I/OMultiplexed data input/output pin.
48,50,51,53
1,3,9,14,27,
VCC/VCC Q-Power supply for internal circuits and input buffers.
43,49
6,12,28,41,
VSS/VSS Q-Ground terminal.
46,52,54
36,40NC-Unused.
2-4 Flash Memory : M29W800AT(Main, IC41)
Pin No.Pin NameI/ODescription
1~8, 16~25,48A0~A18IAddress Inputs
29,31,33,35,
DQ0~DQ7I/O Data Input/Outputs, Command Inputs
38,40,42,44
30,32,34,36,
DQ8~DQ14I/O Data Input/Outputs
39,41,43
45DQ15I/O Data Input/Outputs or Address input
26CE-Chip Enable
28QE-Output Enable
11WE-Write Enable
12RP-Reset/Block Temporary Unprotect
15RY/BYOReady/Busy/Output
47BYTE-Byte/Word Organization
37VCC-Supply Voltage
27,46VSS-Ground
2-5 HEX Inverter (Single Stage) : M74HCU04(IC51)Truth Table
AQ
Pin No.Pin NameI/O Pin Description
LH
1,3,5,9,11,13A0 to A5IData Inputs
2,4,6,8,10,12Q0 to Q5OData OutputsHL
7GND-Ground
14VCC-Positive Supply Voltage
9 |
ACEC
