8081 8081 N/B MN/B Maaintenanceintenance
5.1 Intel Banias Pentium M Processor
Signal Name Type Description Signal Name TypeDescription
INIT# I INIT# (Initialization), when asserted, resets integer registers inside the PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires
processor without affecting its internal caches or floating-point registers. this signal as a clean indication that the clocks and power supplies are
The processor then begins execution at the power on Reset vector stable and within their specifications. ?Clean? implies that the signal will
configured during power on configuration. The processor continues to remain low (capable of sinking leakage current), without glitches, from
handle snoop requests during INIT# assertion. INIT# is an asynchronous the time that the power supplies are turned on until they come within
signal. However, to ensure recognition of this signal following an specification. The signal must then transition monotonically to a high
Input/Output Write instruction, it must be valid along with the TRDY# state. PWRGOOD can be driven inactive at any time, but clocks and
assertion of the corresponding Input/Output Write bus transaction. power must again be stable before a subsequent rising edge of
INIT# must connect the appropriate pins of both processor system bus PWRGOOD.
agents. If INIT# is sampled active on the active to inactive transition of The PWRGOOD signal must be supplied to the processor; it is used to
RESET#, then the processor executes its Built-in Self-Test (BIST) protect internal circuits against voltage sequencing issues. It should be
LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of driven high throughout the boundary scan operation.
all APIC Bus agents. When the APIC is disabled, the LINT0 signal ITP_CLK[1:0] I ITP_CLK[1:0] are copies of BCLK that are used only in processor
becomes INTR, a maskable interrupt request signal, and LINT1 systems where no debug port is implemented on the system board.
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
compatible with the signals of those names on the Pentium processor. implemented on an interposer. If a debug port is implemented in the
Both signals are asynchronous. system, ITP_CLK[1:0] are no connects. These are not processor signals.
Both of these signals must be software configured using BIOS RESET# I Asserting the RESET# signal resets the processor to a known state and
programming of the APIC register space and used either as NMI/INTR invalidates its internal caches without writing back any of their contents.
or LINT[1:0]. Because the APIC is enabled by default after Reset, For a power-on Reset, RESET# must stay active for at least two
operation of these pins as LINT[1:0] is the default configuration. milliseconds after VCC and BCLK have reached their proper
LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically. specifications. On observing active RESET#, both system bus agents
This signal must connect the appropriate pins of both processor system will deassert their outputs within two clocks. All processor straps must
bus agents. For a locked sequence of transactions, LOCK# is asserted be valid within the specified setup time before RESET# is deasserted.
from the beginning of the first transaction to the end of the last RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent
transaction. responsible for completion of the current transaction), and must connect
When the priority agent asserts BPRI# to arbitrate for ownership of thethe appropriate pins of both processor system bus agents.
processor system bus, it will wait until it observes LOCK# deasserted. RSVD - These pins are RESERVED and must be left unconnected on the board.
This enables symmetric agents to retain ownership of the processor However, it is recommended that routing channels to these pins on the
system bus throughout the bus locked operation and ensure the board be kept open for possible future use. Please refer to the platform
atomicity of lock. design guides for more details.
PRDY# O Probe Ready signal used by debug tools to determine processor debug SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to
readiness. enter the Sleep state. During Sleep state, the processor stops providing
PREQ# I Probe Request signal used by debug tools to request debug operation of internal clock signals to all units, leaving only the Phase-Locked Loop
the processor. (PLL) still operating. Processors in this state will not recognize snoops
PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor or interrupts. The processor will recognize only assertion of the
temperature monitoring sensor detects that the processor has reached its RESET# signal, deassertion of SLP#, and removal of the BCLK input
maximum safe operating temperature. This indicates that the processor while in Sleep state. If SLP# is deasserted, the processor exits Sleep
Thermal Control Circuit has been activated, if enabled. state and returns to Stop-Grant state, restarting its internal clock signals
This signal may require voltage translation on the motherboard. to the bus and processor core units. If DPSLP# is asserted while in the
PSI# O Processor Power Status Indicator signal. This signal is asserted when theSleep state, the processor will exit the Sleep state and transition to the
processor is in a lower state (Deep Sleep and Deeper Sleep). Deep Sleep state.
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