8081 8081 N/B MN/B Maaintenanceintenance
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
PCI Interface Signals (Continued) PCI Interface Signals (Continued)
Signal Name Type Description Signal Name Type Description
FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the STOP# I/O Stop: STOP# indicates that the ICH4, as a Target, is requesting the
beginning and duration of a PCI transaction. While the Initiator Initiator to stop the current transaction. STOP# causes the ICH4, as
asserts FRAME#, data transfers continue. When the Initiator an Initiator, to stop the current transaction. STOP# is an output
negates FRAME#, the transaction is in the final data phase. when the ICH4 is a Target and an input when the ICH4 is an
FRAME# is an input to the ICH4 when the ICH4 is the Target, andInitiator. STOP# is tri-stated from the leading edge of PCIRST#.
FRAME# is an output from the ICH4 when the ICH4 is the Initiator. STOP# remains tri-stated until driven by the ICH4.
FRAME# remains tri- stated by the ICH4 until driven by an PERR# I/O Parity Error: An external PCI device drives PERR# when it
Initiator. receives data that has a parity error. The ICH4 drives PERR# when
IRDY# I/O Initiator Ready: IRDY# indicates the ICH4's ability, as an it detects a parity error. The ICH4 can either generate an NMI# or
Initiator, to complete the current data phase of the transaction. It is SMI# upon detecting a parity error (either detected internally or
used in conjunction with TRDY#. A data phase is completed on any reported via the PERR# signal).
clock that both IRDY# and TRDY# are sampled asserted. During a REQ[4:0]# I PCI Requests: The ICH4 supports up to 6 masters on the PCI bus.
write, IRDY# indicates the ICH4 has valid data present on REQ[5]#/ REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the
AD[31:0]. During a read, it indicates the ICH4 is prepared to latch REQ[B]#/ other, but not both). If not used for PCI or PC/PCI,
data. IRDY# is an input to the ICH4 when the ICH4 is the Target GPIO[1] REQ[5]#/REQ[B]# can instead be used as GPIO[1].
and an output from the ICH4 when the ICH4 is an Initiator. IRDY# NOTE: REQ[0]# is programmable to have improved arbitration
remains tri-stated by the ICH4 until driven by an Initiator. latency for for supporting PCI-based 1394 controllers.
TRDY# I/O Target Ready: TRDY# indicates the ICH4's ability, as a Target, to GNT[4:0]# O PCI Grants: The ICH4 supports up to 6 masters on the PCI bus.
complete the current data phase of the transaction. TRDY# is used GNT[5]#/ GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the
in conjunction with IRDY#. A data phase is completed when both GNT[B]#/ other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can
TRDY# and IRDY# are sampled asserted. GPIO[17] instead be used as a GPIO.
During a read, TRDY# indicates that the ICH4, as a Target, has Pull-up resistors are not required on these signals. If pull-ups are
placed valid data on AD[31:0]. During a write, TRDY# indicates used, they should be tied to the Vcc3_3 power rail.
that the ICH4, as a Target, is prepared to latch data. TRDY# is an GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up.
input to the ICH4 when the ICH4 is the Initiator and an output from PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for
the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the all transactions on the PCI Bus.
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4 NOTE: This clock does not stop based on STP_PCI# signal.
until driven by a target. PCICLK only stops based on SLP_S1# or SLP_S3#.
PAR I/O Calculated/Checked Parity: PAR uses ?even? parity calculated on PCIRST# O PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on
36 bits, AD[31:0] plus C/BE[3:0]#. ?Even? parity means that the the PCI bus. The ICH4 asserts PCIRST# during power-up and when
ICH4 counts the number of 1s within the 36 bits plus PAR and the S/W initiates a hard reset sequence through the RC (CF9h) register.
sum is always even. The ICH4 always calculates PAR on 36 bits The ICH4 drives PCIRST# inactive a minimum of 1 ms after
regardless of the valid byte enables. The ICH4 generates PAR for PWROK is driven active. The ICH4 drives PCIRST# active
address and data phases and only guarantees PAR to be valid one a minimum of 1 ms when initiated through the RC register.
PCI clock after the corresponding address or data phase. The ICH4 PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and
drives and tri-states PAR identically to the AD[31:0] lines except may require multiple transactions to complete. ICH4 asserts
that the ICH4 delays PAR by exactly one PCI clock. PAR is an PLOCK# when it performs non- exclusive transactions on the PCI
output during the address phase (delayed one clock) for all ICH4
initiated transactions. PAR is an output during the data phase bus. Devices on the PCI bus (other than the ICH4) are not permitted
to assert the PLOCK# signal.
(delayed one clock) when the ICH4 is the Initiator of a PCI write SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that
transaction, and when it is the Target of a read transaction. ICH4 detects a system error condition. Upon sampling SERR# active, the
checks parity when it is the Target of a PCI write transaction. If a ICH4 has the ability to generate an NMI, SMI#, or interrupt.
parity error is detected, the ICH4 will set the appropriate internal
status bits, and has the option to generate an NMI# or SMI#.
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ACEC
