8081 8081 N/B MN/B Maaintenanceintenance
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
Processor Interface Signals (Continued) Real Time Clock Interface Signals
Signal Name Type Description Signal Name Type Description
CPUPWRGD OD CPU Power Good: This signal should be connected to the RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
processor?s PWRGOOD input. To allow for Intel ? SpeedStep?
RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
technology support, this signal is kept high during an Intel
SpeedStep technology state transition to prevent loss of processor
context. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the ICH4?s Other Clock Signals
PWROK and VGATE / VRMPWRGD signals. Signal Name Type Description
DPSLP# O Deeper Sleep: This signal is asserted by the ICH4 to the processor. CLK14 I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz.
When the signal is low, the processor enters the Deeper Sleep state This clock is permitted to stop during S1-M (or lower) states.
by gating off the processor Core clock inside the processor. When CLK48 I 48 MHz Clock: This clock is used to run the USB controller. It runs
the signal is high (default), the processor is not in the Deeper Sleep
at 48 MHz. This clock is permitted to stop during S1-M (or lower)
state. This signal behaves identically to the STP_CPU# signal, but
states.
at the processor voltage level. CLK66 I 66 MHz Clock: This is used to run the hub interface. It runs at 66
MHz. This clock is permitted to stop during S1-M (or lower) states.
SMBus Interface Signals Miscellaneous Signals
Signal Name Type Description
Signal Name Type Description
SMBDATA I/OD SMBus Data: External pull-up is required.
SPKR O Speaker: The SPKR signal is the output of counter 2 and is
SMBCLK I/OD SMBus Clock: External pull-up is required. internally ?ANDed? with Port 61h bit 1 to provide Speaker Data
Enable. This signal drives an external speaker driver device, which
SMBALERT#/ I SMBus Alert: This signal is used to wake the system or generate
GPIO[11] SMI#. If not used for SMBALERT#, it can be used as a GPI. in turn drives the system speaker. Upon PCIRST#, its output state is
0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap.
RTCRST# I RTC Reset: When asserted, this signal resets register bits in the
System Management Interface Signals
RTC well and sets the RTC_PWR_STS bit (bit 2 in
Signal Name Type Description GEN_PMCON3 register).
INTRUDER# I Intruder Detect: Can be set to disable system if box detected open.NOTES:
This signal?s status is readable, so it can be used like a GPI if the 1. Clearing CMOS in an ICH4-based platform can be done by using
Intruder Detection is not needed. a jumper on RTCRST# or GPI, or using SAFEMODE strap.
SMLINK[1:0] I/OD System Management Link: SMBus link to optional external Implementations should not attempt to clear CMOS by using a
system management ASIC or LAN controller. External pull-ups are jumper to pull VccRTC low.
required. 2. Unless entering the XOR Chain Test Mode, the RTCRST# input
Note that SMLINK[0] corresponds to an SMBus Clock signal, and must always be high when all other RTC power planes are on.
SMLINK[1] corresponds to an SMBus Data signal.
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