DV-S353
IC TERMINAL DESCRIPTION
PIN CONFIGURATION (Top view)
K4S641632D (SDRAM)
VDD154VSS
DQ0253DQ15
VDDQ352VSSQ
DQ1451DQ14
DQ2550DQ13
VSSQ649VDDQ
DQ3748DQ12
DQ4847DQ11
VDDQ946VSSQ
DQ51045DQ10
DQ61144DQ9
VSSQ1243VDDQ
DQ71342DQ8
VDD1441VSS
LDQM1540N.C/RFU
WE1639UDQM
CAS1738CLK
RAS1837CKE
CS1936N.C
BA02035A11
BA12134A9
A10/AP2233A8
A02332A7
A12431A6
A22530A5
A32629A4
VDD2728VSS
PIN FUNCTION DESCRIPTION
PinNameInput Function
CLKSystem clockActive on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CSChip select
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKEClock enableCKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
A0 ~ A11Address
Row address : RA0 ~ RA11, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
BA0 ~ BA1Bank select address
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
RASRow address strobe
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
CASColumn address strobe
Enables column access.
Enables write operation and row precharge.
WEWrite enable
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
L(U)DQMData input/output mask
Blocks data input when L(U)DQM active.
DQ0 ~ 15Data input/outputData inputs/outputs are multiplexed on the same pins.
VDD/VSSPower supply/groundPower and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
VDDQ /VSSQData output power/ground
immunity.
No connection
N.C/RFUThis pin is recommended to be left No Connection on the device.
/reserved for future use |
ACEC
