MEMORY DEVICES
Each memory device has the following data.
1 RAM1 :
S-RAM for operation program, Register, Pattern and
Song. (Upper part of data bus)
CPU
Internal Memory2 Internal ROM of CPU :
2 ROM 512 kbitMain program data for system operation
RAM1
3 RAM 16 kbit
1
3 Internal RAM of CPU :
LSI91 Mbit
Work area for system operation
LSI8
4 ROM1 :
Demo, Accompaniment data, Song, Pattern, Synth mode
ROM1
4
5 ROM2 :
8 Mbit
Sound Waveforms/Tone data Digital sound effect
LSI2
DSP
6 Working RAM :
ROM2Work area for DSP
5
LSI432 Mbit
LSI3
Working RAM
6
256 kbit
LSI5
RESET CIRCUITDVDD
DSP
HG51B155FD
Battery setVDD
VDDLSI4
RESB
RESETRESET
RESPB0
PW/SW ON
CPURESET
DVDD
HD6473042F16-463
LSI9RESB
APO
Key Controller
PWSWAPO
TC190C020AF-001
NMIPA7DVDD
LSI10
From power switch(5V)
Power Supply
DVDD
Circuit
Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5 V to generate DVDD voltage, then raises RESET signal to +5 V. During this period the
DSP and the key controller LSI initialize their internal circuits.
N 9 N |
ACEC
