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System clock & reset for power management
ANo.Pin NameI/OFunction
System clock input or Oscillator input
5XT1/SCLKIApply 48 MHz clock input or connect 30 MHz X'tal.
Clock frequency is selected by "CLKSEL" signal.
IF 48 MHz clock input is applied to SCLK, this signal must be opened. Otherwise,
6XT2O
connect to 30 MHz X'tal. Clock frequency is selected by "CLKSEL" signal.
10VCCRST0IReset for Power management.
USB interface
No.Pin NameI/OFunction
B
USB's D+ high-speed signal
114, 157, 151, 132, 126 DP (5 : 1)I/O
Shared with DMx pins having the same numbers.
USB's D+ full-speed signal
115, 158, 152, 133, 127 RSDP (5 : 1)O
Connected to DPx through 36 & 5% precision Rs resistor.
USB's D� high-speed signal
112, 155, 149, 130, 124 DM (5 : 1)I/O
Shared with DPx pins having the same numbers.
USB's D� full-speed signal
111, 154, 148, 129, 123 RSDM (5 : 1)O
Connected to DMx through 36 & 5% precision Rs resistor.
Pin for inputting the overcurrent status of the USB Root Hub Port
C
95, 97, 99, 96, 93OCI (5 : 1)1 : No power supply problemI
2 : Overcurrent has occurred
Power supply control output for USB Root Hub Port
107, 105, 103, 102, 94PPON (5 : 1)0 : Power supply OFFO
1 : Power supply ON
System interface
No.Pin NameI/OFunction
System management inturrupt output
D11SMI0O0 : Interrupt occurs
1 : Interrupt does not occur
Clock signal select
109CLKSELI1 : XT1/SCLK must be applied 48 MHz clock input
0 (Default) : XT1/SCLK must be connected to 30 MHz X'tal
91SRCLKOSerial ROM Clock out
90SRDTAI/OSerial ROM Data
Serial ROM Input Enable
92SRMODI0 (Default) : Serial ROM Inactive
1 : Serial ROM Active
E
Chip clock typeCLKSELOn board setting
Use 48 MHz clock input148 MHz clock signal supply to XT1/SCLK on board
30 MHz X'tal connects between XT1/SCLK and XT2. Also, the capacitor and some
Use 30 MHz Oscillator0
other element must be required.
F
86DVR-810H-S
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ACEC
