IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36705TQC (Micro Controller)
Pin FunctionPin
NumberName
81SI2/PF5[SI2] UART2 data input. This input is used from time to time while input operation is selected.
Therefore, it is needed to stop output by other functions except when such output is performed intentionally.
[PF5] Denerel-purpose I/O port.
82SO2/PF6[SO2] UART2 data output. This function is valid when UART2 data output is enabled.
[PF6] General-purpose I/O port. This function is valid when UART2 data output is disabled.
83PF7/INT4/ATGX[INT4] Input of external interrupt request. This input is used front time to time while the corresponding
external interrupt is enabled. Therefore, it is needed yo stop output by other functions except when such
output is performed intentionaly.
[ATGX] External trigger input for A/D converter. This input is used from time to time when this pin is selected
for the A/D start cause. Therefore, it is needed to stop output by other functions excep when such output is
performed intentionally.
[PF7] General-purpose I/O port.
72AN0/STRBIN[AN0] A/D converter analog input. This input is used from time to time while input operation is selected.
/PD0Therefore, it is needed to stop output by other functions except when such output is performed intentionally.
[STRBIN] The clocksource input for DVDSOS logic. This input is used from time to time while input
operation is selected. Therefore, it is needed to stop output by other functions except when such output is
performed intentionally.
[PD0] General-purpose I/O port.
5CLK/PA6System clock output. The pin outputs the same clock frequency as the external bus operating frequency.
[PA6] When the pin is not used for this purpose, it can be used as a general-purpose I/O port.
96RAS0/PB0RAS output of DRAM bank 0
97CS0L/PB1CASL output of DRAM bank 0
98CS0H/PB2CASH output of DRAM bank 0
99DW0X/PB3WE output of DRAM bank 0
100RAS1/PB4/EOP2RAS output of DRAM bank 1
CASL output of DRAM bank 1
1CASH output of DRAM bank 1CS1L/PB5
WE output of DRAM bank 1/DREQ2
2CS1H/PB6
See the description of the DRAM interface for more information./DACK2
[EOP2] DMAC EOP output (ch 2). This function is valid when DMAC EOP output is enabled.
3DW1X/PB7
[DREQ2] Input of DMA external transfer request. This input is used from time to time when this pin is
selected for the DMAC transfer cause. Therefore, it is needed to stop output by other functions except
when such output is performed intentionally.
[DACK2] Output of DMAC external transfer reques acceptance (ch 2). This function is valid when the
output of DMAC transfer request acceptance is enabled.
[PB0-7] When each pin is not used for the corresponding purpose, the pin can be used as a general-
purpose I/O port.
16MD0Mode pins 0 to 2. Use these pins to setting the basic MCU operation Mode.
17MD1Connect these pins directly to Vcc or Vss.
18MD2
92X0Clock (Oscillator) input
91X1Clock (Oscillator) output
14RSTXExternal reset input.
13HSTXHardware Standby input.
12NMIXNon-maskable interrupt (NMI) input (active-low).
95INT0/PE0[INT0,1] Input of external interrupt request. This input is used from time to time while the corresponding
94INT1/PE1external interrupt is enabled. Therefore, it is needed to stop output by other functions except when such
output is performed intentionally.
[PE0,1] General-purpose I/O ports.
- 36 - |
ACEC
