IC BLOCK DIAGRAM & DESCRIPTIONIC BLOCK DIAGRAM & DESCRIPTION
IC822 K4S161622D(DRAM)IC870 LC708746V(DAC)
SCKIML/I2SMC/IWLMD/DMMODEMUTE
LWE212131489
LC708746V
Data Input Register
14 LDQMCONTROL
I/O Control
INTERFACE
Bank SelectFMT(1:0)IWL(1:0)LRPBCPMUTEPDWNATCPL(3:0)UPDATELxA(23:0)RxA(23:0)DEEMPHPDWNPDWNPDWN
512K x 16
L0A(7:0)
2,3,5,6,7,8,9,11,
12,39,40,42,43, DQ1
25OUT0L
45,46,48,49DigitalSigmaStereo
CLK 35512K x 16BCKIN 3Delta26Sense AMPGR0FilterDAC
Row BufferRow DecoderOutput BufferModulator27OUT0R
LRCIN 4
Refresh Counter
20~24,LRCIN2 10
ADDR0A(7:0)
27~32
L1A(7:0)
Column Decoder
Address Register
21OUT1L
DACSigma
AUDIODigitalStereo
CHANNELDelta22GR1
LCBRLRASINTERFACEFilterDAC
Latency & Borst LengthCONTOLModulator23OUT1R
Col. BufferR1A(7:0)
LCKEDIN05L2A(7:0)Programming Register
DIN1617OUT2L
LRASLCBRLWELDQMSigma
LCASLWCBRDigitalStereo
DIN27Delta18GR2
FilterDAC
Modulator
19OUT2R
Timing Register
R2A(7:0)
1112024281516
35341817161536
DVDDDGNDAGND1AGND2AVDD1AVDD2CAP
CLKCKECSRASCASWEL(U)DQM
Pin No.NameType Function
1DVDDSupplyDigital power source
Pin NAME Input Function
2SCKIDigital inputSystem clock input
3BCKINDigital inputAudio data bit clock input
CLKSystem ClockActive on the positive going edge to sample all inputs.
4LRCINDigital inputSampling rate clock (LRCK) input
5DIN0Digital inputChannel 0 Serial audio data input
Disables or enables device operation by masking or enabling all inputs except
CSChip Select
CLK,CKE and L(U)DQM6DIN1Digital inputChannel 1 Serial audio data inout
7DIN2Digital inpiutChannel 2 Serial audio data input
Masks system clock to freeze operation from the next clock cycle.8MODEDigital inputControl mode select
CKEClock EnableCKE should be enabled at least one cycle prior to new command.Internal pull-upLow= Software mode
Disable input buffers for power down in standby.High= Hardware mode
9MUTEDigital bidirectionalMute control (PCM mode)
AddressRow/column addresses are multiplexed on the same pins.
A0 - A10/APInput Output (Auto mute active)
Row address : RA0 - RA10, Column address : CA0 - CA7
Low; Not mute Low; Mute off
High; Mute High; Mute on
Bank Select AddressSelects bank to be activated during row address latch time.
BAZ; Auto mute
Selects bank for read/write during column address latch time.
10LRCIN2Digital input192kHz/96kHz Mode active 2nd LRCIN input
Row Address StrobeLatches row addresses on the positive going edge of the CLK with RAS low.Internal pull-down
RAS
Enables row access & precharge.11DGNDSupplyDigital GND
12ML/I2SDigital inputSoftware mode; 3way serial control latch lag
Column Address StrobeLatchea column addresses on the positive going edge of the CLK with CAS low.Internal pull-upHardware mode; Input format selector
CAS
Enables column access.13MC/IWLDigital inputSoftware mode; 3way serial control clock input
Internal pull-upHardware mode; Input word length select
Write EnableEnables write operation and row precharge.
WE14MD/DMDigital inputSoftware mode; 3way serial control data input
Latches data in starting from CAS, WE active.
Hardware mode; Deepnhasis select
15AVDD2SupplyAnalogue power source
Data Input/Output MaskMskes data output Hi-Z, ISHZ sfter the clock and masks the output.
L(U)DQM16CAPAnalogue outputAnalogue power VREF de-coupling
Blocks data input when L(U)DQM active.
17OUT2LAnalogue outputLch 2 Output
DQ0 - 15Data Input/OutputData inputs/outputs are multiplexed on the same pins.18GR2Analogue inputCh 2 GND
19OUT2RAnalogue outputRch 2 Output
VDD/VSSPower Supply/GroundPower and ground for the input buffers and the core logic.20AGND1SupplyAnalogue GND
21OUT1LAnalogue outputLch 1 Output
Isolated power supply and ground for the output buffers to provide improved noise22GR1Analogue inputCh 1 GND
VDDQ/VSSQ Dsta Output Power/Ground
immunity.
23OUT1RAnalogue outputRch 1 Output
24AGND2SupplyAnalogue GND
No Connection/
N.C/RFUThis pin is recommended to be left No Connection on the device.25OUT0LAnalogue outputLch 0 Output
Reserved for Furure Use
26GR0Analogue inputCh 0 GND
27OUT0RAnalogue outputRch 0 Output
28AVDD1SupplyAnalogue power source
- 32 -- 33 - |
ACEC
