DV-L78U
9-9. IC601 IX1608GE
Pin No.Pin nameTypeI/OFunction
Host interface, CD-DSP interface, subcode interface (32-pin)
Reset input (active low). When deassert is applied in the asserted state, the
141RESET#II
initializing process of MD36710X is started.
Stand-by input (active low). When it is asserted together with RESET#, all output
pins and bidirectional pins are floated to separate MD36710X electrically from the
130PWRDN#IIperipherals. The inner operation is wholly stopped to also minimize the power
consumption.
In the stand-by mode, the contents of SDRAM are not held.
142IDLE3-SOIdle, init or reset state display output (active high)
The data bus width of the host interface is determined. Only during reset,
35HWIDIIchange is possible. For the low level (GND), the host interface of MD36710X
is set to 8 bits but set to the 16-bit width for the high level (VDD).
In the 16-bit width mode (HWIS is VDD), the byte order of the data bus of the host
interface is determined.
36HORDIIItcan be changed only during reset. MD36710X is set to input or output m.s. bytes
at HD [15:8] for the low level (GND) and at HD [7:0] for the high level (VDD).
When HWID is at the GND level, it is connected to GND.
The protocol of the host bus is determined. It can be changed only during reset.
37HTYPEIIMD36710X is set to the type A for the low level (GND) and to the type B for the high
level (VDD).
8 l.s. of the host data bus. When HWID input is connected to GND, only the 8 l.s. signal
12, 14~17,
HD[7:0]3-SI/Ois defined as the host data signal. When HWID is connected to VDD, it is defined
19~21
as the 8 l.s. line of 16-bit data bus.
When HWID is connected to VDD, it becomes the data line 11:8 of the 16-bit host data
7, 9~11HD[11:8]3-SI/O
bus. When HWID is connected to GND, it becomes NC pin as specified below.
7NC (HD[11])OOFor test (output)
9NC (HD[10])IIFor test (input)
10NC (HD[9])IIFor test (input)
11NC (HD[8])IIFor test (input)
When HWID is connected to VDD, it becomes the data line 15:12 of the 16-bit host
3~6HD[15:12]3-SI/Odata bus. When HWID is connected to GND, it becomes CD-DSP serial input port pin
as specified below.
6CDDAT (HD[12])IICD-DSP bit clock input
5CDDAT (HD[13])IICD-DSP data input
4CDFRM (HD[14])IICD-DSP LR clock (frame) input
3CDERR (HD[15])IICD-DSP data error input
22,Host address input. The address signal to specify the physical address in
HA[3:0]II
24~26MD36710X is input.
29HCS#IIHost chip select input. Active low
Host protocol A type (HTYPE = GND): HR/W#. Input to determine the host access
27HWR# (HR/W#)II
direction. Host protocol B type (HTYPE = VDD): HWR#. Host write input (active low).
Host protocol A type (HTYPE = GND): HDS#. Data strobe input (active low).
30HRD# (HDS#)II
Host protocol B type (HTYPE = VDD): HRD#. Host read input (active low).
Host ready output (active high). To transfer the stream via the host bus using this
signal, use this signal. Moreover, the external pull-up resistor is necessary.
31HRDY3-SOIt is possible to check that the transfer of CodBurstLen byte length is regarded as one
packet and the signal is active before start of transfer of each packet and continuously
write the bit stream up to CodBurstLen into MD36710X.
Interrupt request (Active low). It is deasserted as the host leads the interrupt status
register of MD36710X. Moreover, it is also deasserted after the host masks or resets
34HIRQ#3-SOthe interrupt with the interrupt mask register of MD36710X.
If HIRQ# is not asserted, it enters the 3-state state. (The external pull-up resistor is
necessary.)
Host acknowledge output (active low). For the protocol of type A, MD36710X asserts the
output to inform the end of the read or write cycle.
If the signal is not active, it enters the 3-state state. (The external pull-up resistor is
32HACK#3-SO
necessary.)
For the protocol of type B, it functions as the wait output signal. If the high-speed host
(microcomputer) is used, it is sometimes unnecessary to connect the signal.
31 |
ACEC
