UX-A450DE/IT/H
NX-A550DE/IT/FO-A650IT
[2] Circuit description of control PWB4) External RAM and ROM
Moveable and programmble size external SRAM memory of up to 1 MB,
1. General descriptionDRAM memory of up to 4 MB, and ROM of up to 2 MB can be directly
connected to the SCE214V. By using an external address decoder, the
Fig. 2 shows the functional blocks of the control PWB, which is com-size of SRAM and/or ROM can be extened. The ROM stores all the
posed of 4 blocks.program object code.
5) Flash Memory Controller
(1) SCE214V
The SCE214V includes a flash memory controller that supports NOR,
IA(20438)(2) FLASH
NAND, and Serial NAND-type flash memory. The supported size of NOR-
MEMORY(SRAM) ROMtype memory is up to 1 MB and the supported size of NAND-type memory
is unlimited.
(3) DRAM6) Stepper Motor Control
Eight outputs are provided to external current drivers: four to the scan-
ner motor and four to the printer motor. The stepping patterns are pro-
(4) FLASHgrammable and selectable line times are supported. A timeout circuit
MEMORYcontrols the power control of the motors. The printer or scanner motor
outputs can be programmed as GPOs for applications using single mo-
tor or paper printers.
Fig. 2 Control PWB functional block diagram
7) T.4/T.6 Compressor/Decompressor
2. Description of each block
MH, MR and MMR compression and decompression are provided in
hardware. T.4 line lengths of up to 8192 pixels are supported. MMR and
(1) Main control block
Alternating Compression/Decompression (ACD) on a line by line basis
The main control block is composed of CONEXANT 1 chip fax engineprovide support for up to three independent compression and decom-
(SCE214V), FLASH ROM (2Mbit), DRAM (4Mbit) and FLASH MEMORYpression processes.
(4Mbit).
Devices are connected to the bus to control the whole unit.8) Bi-level Resolution Conversion
1) SCE214V (IC3) : pin-176 QFP (FAX CONTROLLER)One independent programmable bi-level 1D-resolution conversion block
is provided to perform expansion or reduction on the T.4 decompressed
1 chip fax engine has Internal Integrated Analog (20438) and Internal
data and scan image data. Image expansion can be programmed up to
memory (SRAM : 32kbit).200% and reduction down to 33%. Vertical line ORing and data output
2) SST39VF020P (IC1): pin-32 TSOP (FLASH ROM)bit order reversal is also provided.
FLASH of 2Mbit equipped with software for the main CPU.9) Printer IF
3) MSM51V4800E (IC2): pin-28 SOJ (DRAM)The Printer Interface provides a standard connection between the
SCE214V and a thermal printhead to support thermal printing or thermal
Y Image memory for recording process.
transfer. The thermal printer interface consists of programmable data,
Y Memory for openLCR function.latch, clock, and up to four strobe signals. Programmable timing sup-
ports traditional thermal printers, as well as the latchless split mode print-
4) K9F4008W0A (IC8): pin-44 TSOP (FLASH MEMORY)ers, and line lengths of up to 2048 pixels. Line times from 5 ms to 40 ms
A 512 k x 8bit NAND FLASH MEMORY to store the voice and imageare supported.
data when using memory function.The SCE214V includes a thermal ADC (TADC) function utilizing a D/A
converter and a comparator to monitor the printhead temperature. Ex-
(2) IC3 (SCE214V) Hardware descriptionternal terminating resistors must be supplied; the values are determined
by the specific printhead selected.
A) CONTROL BLOCKAs an option, plain paper inkjet printing can be supported.
1) Integrated Controller (SCC)
The Controller contains an internal MC24 Processor with a 16-MB ad-10) TPH Hardware Timer
dress space and dedicated circuitry optimized for facsimile imageThe TPH hardware timer provides a 500 ms timer that can be re-trig-
processing and monitoring and for thermal or thermal transfer printergered or reset.
support.11) Scanner and Video Control
The CPU provides fast instruction (up to 10 MHz clock speed) execu-
tion and memory efficient input/output bit manipulation. The CPU con-Five programmable control and timing signals support common CCD
nects to other internal functions over an 8-bit data bus and 24-bit ad-and CIS scanners. The video control function provides signals for con-
dress bus and dedicated control lines.trolling the scanner and for processing its video output. Three program-
The 24-bit external address bus, 8-bit data bus, control, status and de-mable control signals (START, CLK1n, and CLK2) provide timing re-
coded chip select signals support connection to external ROM, SRAM,lated to line and pixel timing. These are programmable with regard to
DRAM, and FLASH memory.start time, relative delay and pulse width.
Two video control output siganls (VIDCTL[1:0]) provide digital control
2) DRAM Controllerfor external signal pre-processing circuitry. These signals provide a per
The CX06835 includes a DRAM controller with signal and page modepixel period, or per line period, timing with programmable polarity con-
access support which supports fast, normal, or slow refresh time. DRAMtrol for each signal.
memory space is provided in one block up to 4 MB. A maximum of 4 MB
of DRAM is supported. This space has a programmble size and starting
address. Refresh is performed automatically and is supported in stand-
by mode. CAS and RAS signal support is provided for one-DRAM banks
for both 4-bit and 8-bit organizations. Access speeds from 50ns to 70ns
can be supported.
3) DMA Channels
Six internal DMA channels support memory access for scanner, T.4/T.6,
and resolution conversion. DMA Channel 2 can be reprogrammed for
external access to thermal printing, thermal transfer, or plain paper inkjet
printing.
5 � 2 |
ACEC
