4-4. VE-31 Board
The VE-31 video processor board accepts digitized video
and record timing signals from either the AIF-4 board or
DIF-24 board (will be on the market in the near future) and
processes this video for transfer to the BKDE-560 hard disk
drives via the SY-200 board. In addition, the VE-31 board
accepts two playback data streams from the hard disk drives
via the SY-200 board and processes the data for output by
the AIF-4 board or DIF-24 board. DMA transfer bus and
CPU control are received from the SY-200 board and play-
back timing signals are received from the SG-223 board.
Input (record) video data is written into the field sync
(IC25E, IC26E).
This field buffer serves as a ?15 line time base corrector.
Under CPU control, input video 1/2 line blanking can be
eliminated using line memory (IC15C, IC16C). The time
base corrected video can be written directly to transfer
buffer A via tri-state buffer D, or can be compressed.
The compression circuit consists of optional vertical
decimation and raster-to-block conversion (IC22F, IC22H,
IC24H) followed by JPEG compression (IC10F). The 8 bit
data stream is converted to 16 bit width (IC10FF, IC12FF)
and written to transfer buffer A.
4-84-8BKDE-550 |
ACEC
