The 74.25 MHz clock for the Y signal frequency converted
by IC102 is output fr`��� . om pin The 37.2 MHz clocB k for P
and PR is connected to D/A from pin `��� .
IC104 is the D/A for the Y signal. Y signals subjected to D/A
are output fr@com pin . The output level is adjusted by RV101.
IC106 is the D/A for the PB and PR signals. PB and PR signals
subjected to D/A are output fr^1 and om pins %a. The output
level of PB and PR is adjusted by RV103 and RV102.
The Y signal output from IC104 is passed through the low
path filter (FL101), amplified by Q104 and Q105, and con-
nected to the delay line (DL101). After this, they are once
again amplified by Q108 and Q109, and output via the buffer
(Q110). The B and PPR signals subjected to D/A at IC106 are
passed through the low pass filter (FL102, and 103), ampli-
fied by Q122, Q123, Q117, and Q118, passed through the
buffer (Q124, Q119), and output.
The H SYNC and V SYNC generated at IC102 are passed
through the filter and buffer (Q111 to Q114) and output.
3-2 |
ACEC
