IC
HM530281-25(HITACHI)FLAT PACKAGELF2242QC-33(LOGICDEV)FLAT PACKAGE
HM530281RTT-25C-MOS 12 / 16-BIT HALF-BAND INTERPOLATING / DECIMATING DIGITAL FILTER
331,776WORDX8-BIT FRAME MEMORY
NTOP VIEWN
-TOP VIEW-
44
43
42
41
40
39
38
37
36
35
3434
SO15
42
SI11
1
44
31
SI10
43
SO14
DI0
DO0
DI0
1
44
DO0
2
43
30
SI9
44
SO13
DI1
DO1
3
42
29
1
DI1
2
43
DO1
DI2
DO2
1
GND33
GNDSI8
SO12
4
41
28
SI7
SO11
2
DI2
3
42
DO2
5
40
DI3
DO3
2
VDD (+5V)32
27
SI6
SO10
3
DI4
DO4
3
31
DI3
4
41
DO3
6
DI5
DO5
39
26
SI5
SO9
4
7
38
4
30
25
SI4
SO8
5
DI4
5
40
DO4
8
DI6
DO6
5
29
24
37
SI3
SO7
8
DI7
DO7
DI5
6
39
DO5
6
GND28
21
SI2
SO6
9
11
7
VDD (+5V)27
20
10
DI6
7
38
DO6
WE
OE
34
8
SI1
SO5
26
19
SI0
SO4
11
DI7
8
37
DO7
13
WCK
RCK
32
9
25
SO3
12
9
GND
GND
36
12
CGR
33
CGW
10
1124
VDD (+5V)36
CLK
SO2
13
14
31
2338
14
INT
SO1
10
VCC
(+5V)VCC
(+5V)35
18
27
WRS
RRS
39
DEC
SO0 15
WAS
RAS
GND
WE IN
11
34
OE IN
19
26
37
SYNC
WAD
RAD
40
CGW IN
12
33
CGR IN
15
30
WLRS
RLRS
TCO
17
28
12
13
14
15
16
17
18
19
20
21
2241
OE
WCK IN
13
32
RCK IN
16 29WWND
RWND
WCLRRCLR
WRS IN
14
31
RRS IN
16
RND2
17
WLRS IN
15
30
RLRS IN
18RND1
CGR
; READ CLOCK GATE
RND0
WCLR IN
16
29
RCLR IN
CGW
; WRITE CLOCK GATE
DI0 � 7
; DATA INPUTS
WWND IN
17
28
RWND IN
DO0 � 7
; DATA OUTPUTS
(VDD = +5V)
WAS IN
18
27
RAS IN
MODE0 � 1
; MODE SELECT INPUTS
OE
; OUTPUT ENABLE INPUT
PIN
PIN
PIN
PIN
SIGNALSIGNALSIGNALSIGNAL
WAD IN
19
26
RAD IN
RAD
; READ ADDRESS
No. I/ONo. I/ONo. I/ONo. I/O
RAS
; READ ADDRESS SET
MODE0 IN
20
25
TEST1 IN
RCK
; READ CLOCK INPUT
1
O
SO12
12
O
SO3
23
N
VDD
34
I
SI11
2
O
SO11
13
O
SO2
24
I
SI3
35
N
GND
MODE1 IN
21
24
TEST2 IN
RCLR
; READ CLEAR
3
O
SO10
14
O
SO1
25
I
SI4
36
I
CLK
RLRS
; READ LINE RESET
TEST0 IN2223TEST3 INRRS
; READ RESET
4
O
SO9
15
O
SO0
26
I
SI5
37
I
SYNC
RWND
; READ WINDOW MODE
5
O
SO8
16
I
RND2
27
I
SI6
38
I
INT
TEST0 � 3
; TEST INPUTS
6
N
GND
17
I
RND1
28
I
SI7
39
I
DEC
WAD
; WRITE ADDRESS
7
N
VDD
18
I
RND0
29
I
SI8
40
I
TCO
WAS
; WRITE ADDRESS SET
8
O
SO7
19
I
SI0
30
I
SI9
41
I
OE
WCK
; WRITE CLOCK INPUT
WCLR
; WRITE CLEAR
9
O
SO6
20
I
SI1
31
I
SI10
42
O
SO15
WE
; WRITE ENABLE INPUT
10
O
SO5
21
I
SI2
32
N
VDD
43
O
SO14
WLRS
; WRITE LINE RESET
11OSO422NGND33NGND44OSO13
WRS
; WRITE RESET
WWND; WRITE WINDOW MODE
INPUT
CLK
; MASTER CLOCK
32-WORD
32-WORD
32-WORD
32-WORD
DEC
; DECIMATION CONTROL
X8X8X8X8
INT
; INTERPOLATION CONTROL
OE
; OUTPUT ENABLE
READ DATA BUFFER
READ DATA REG.RND0-RND2
; ROUNDING CONTROL
SI0-SI11
; DATA INPUTS
MEMORY ARRAY
1�8
37�44SYNC
; SYNCHRONIZATION CONTROL
TCO
; TWO'S COMPLEMENT FORMAT CONTROL
DI0 � 7
DO0 � 7
1152 DOT X 288 LINE X 8*
1024 DOT X 324 LINE X 8*
OUTPUT
WE 11WRITE DATA REG.10368 DOT X 32WORD X 8* 34 OESO0-SO15; DATA OUTPUTS
WRITE DATA BUFFER
MODE SELECTION
INT DECMODE
00PASS-THROUGH *
32
WCK
13
WRITE
MEMORY
READ
RCK
01INTERPOLATE
COUNTERCONTROLLERCOUNTER
10DECIMATE* Input and output registers run at
12
33
CGW
CGR
11PASS-THROUGH * full clock rate.
14
31
WRS
RRS
0
; LOW LEVEL
REFRESH
1; HIGH LEVEL
18
COUNTER27
WAS
RAS
19
26
WAD
RAD
RND0-RND2 18, 17, 163
15
30
WLRS
RLRS
TCO 40
17
NOTE :
28
WWND
RWND
* Select for MODE PIN (20, 21)
1629
WCLRRCLR
3
19�21,
15�8,
24�31,
5�1,
34ROUND
44�42
SI0-SI11INTER-
121255-TAP
FIR
AND
16DECI-
MATION
POLATION
16 SO0-SO15
CIRCUITFILTERLIMIT
CIRCUITCIRCUIT
3
CLK 363
INT 38
DEC 39
SYNC 37
OE 41
BKPF-131B5-17 |
ACEC
