6-7. BUF2 Board
The BUF board has two functions: digital uniformity control and digital convergence control. The digital
uniformity control improves non-uniformity of brightness between CRTs.The digital uniformity
control is realized by sending dynamic correction signals to the GAIN control input of R, G, and B
channel on the BK (VIDEO OUT) board corresponding to the respective display positions. A uniform
white display can be obtained from center to corners of screen. The digital convergence control is the
conversion adjustment function that enables individual conversion adjustment at very many positions on
the screen independently so that the optimum conversion is realized at each position on display by
sending unique correction signals of HDC, VDC, HMC and VMC to the DC board in which output circuit
is contained, depending on the screen positions and finally by driving CY.
1. Interface
Interface between the BUF2 board and the SUB CPU (IC1001) is established by the three wire bus serial
communication with the main CPU on the BC (system control) board using MISO, MOSI, SCLK.
Switching between PLD IC101 (for digital uniformity) and IC201 (for digital convergence) is performed
by the _CS signal coming from SUB CPU.
Connector CN003 is prepared for factory setup that is used to write down and read out data to and from
PLD internal register using the parallel signals of A3-0, D7-0, _WR, _RD and _CS.
The data such as a board ID is stored in EEP ROM IC1003.
2. SRAM memory specifications
8-bit data (horizontally 32 x vertically 16) for each R, G and B channel, for all formats and for each scan
is stored in SRAM IC102 (for digital uniformity correction). Also 8-bit data (horizontally 32 x vertically
16) for HDC, VDC, HMC and VMC respectively is stored in SRAM IC202 (for digital convergence
correction). Note that data amount equivalent to several blocks are blanked in the top, bottom, right or left
of a screen in the effective video signal period because the data is 32 x 16 including the blanking period.
OFormat and scan can be switched by specifying SRAM address MA16-11.
Each SRAM is backed up by lithium battery.
3. PLL
The AFC P signal from deflection circuit and the H. OUT signal from the H-address generator circuit
inside PLD (IC101) are inputted to PLL IC105 that generates the fundamental CLK for data processing
circuit. The fundamental CLK is 512 x fH (15 k is 1024 x fH) where fH is horizontal deflection frequen-
cy.
4. Data processing circuit
The digital uniformity and digital conversion control are implemented by accessing to the respective
SRAMs using H8-0 and V3-0 (after converting into A10-0 inside PLD) that are generated by the H-address
and V-address generator circuits corresponding to the raster scanning in each PLD IC, thus reading out
the specified data. The read-out data is D/A converted to analog data that passes through low-pass filter
and clamp circuit, and is outputted as offset waveform. Data in the vertical direction is created by linear
interpolation between the upper data and lower data. Using the vertically interpolated data, data in the
horizontal direction is also linear-interpolated from the previous and following data to realize the horizon-
tal interpolation.
Real time processing is required for normal data read-out. However, because re-writing data is required
during adjustment, writing-down is performed by interrupt processing that stops reading data from
SRAM.
6-18BVM-D32E1WA/D32E1WE/D32E1WU |
ACEC
