? MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER)
Pin No.Pin NameI/ODescription
1, 2NCONot used (open)
3NCINot used (fixed at OL�)
4REQORequest signal output to the system controller (IC201) OL� active
5CCLKISerial data transfer clock signal input from the system controller (IC201)
6CSIISerial data input from the system controller (IC201)
7CSOOSerial data output to the system controller (IC201)
8SCLKOClock signal output for subcode data reading to the CXD2530Q (IC101)
9SSII Subcode data input from the CXD2530Q (IC101)
10NCONot used (open)
11 to 18ADD0 to ADD7OAddress signal output to the S-RAM (IC502)
19NCINot used (fixed at OL�)
20 to 27DATA0 to DATA7 I/O Two-way data bus with the S-RAM (IC502)
System reset signal input from the system controller (IC201), SONY bus interface (IC302) and
28RSTIreset signal generator (IC304) OL�: reset
For several hundreds msec. after the power supply rises, OL� is input, then it changes to OH�
29EXTALISystem clock input terminal (10 MHz)
30XTALOSystem clock output terminal (10 MHz)
31VSSNGround terminal
32 to 55NCO Not used (open)
56BUSYOBusy signal output to the system controller (IC201) OL�: busy status
57 to 61NCO Not used (open)
62CEOChip enable signal output to the S-RAM (IC502) OL� active
63WEOData write enable signal output to the S-RAM (IC502) OL� active
64 to 69ADD8 to ADD13 OAddress signal output to the S-RAM (IC502)
70VDDNPower supply terminal (+5V)
71NCONot used (open)
72NCINot used (fixed at OL�)
73NCINot used (fixed at OH�)
74ADD14OAddress signal output to the S-RAM (IC502)
75NCONot used (open)
76SCORISubcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
77WFCKIWrite frame clock (7.35 kHz) signal input from the CXD2530Q (IC101)
78BUCKIBackup power supply detection signal input terminal (used also to reset standby)
79, 80NCI Not used (fixed at OL�)
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