2-6. ESP (Electronic Shock Protection) Circuit
Figure 2-11 shows the ESP (Electronic Shock Protection) circuit block diagram.
(1) Generation of DA DATA
The signals of A to D that are picked up by the detectors of the optical pickup, are input to the RF gnal isAMP IC501 where the EFM si
generated by the RF AMP inside IC501. The EFM signal thus generated is output to pin3 [EFM] of the DSP IC502 fr!¤ [EFM]om pin
of IC501. In the DSP IC502, various signal processing (14-8 demodulation, de-interlead on theving, error correction, etc.) is performe
input EFM signal to generate the DA DATA. The DA DATA thus generated is output to the D-RAM CONTROLLER IC601 with the L-
ch data and the R-ch data alternately, in synchronization with LRCK (L-channel/R-channel discrimination signal) thafromt is output
pin^Y [LRCK] of DSP IC502, and also in synchronization with BLCK (bit clock) that is output from pin&1 [BCLK]. The BCLK (48fs)
and LRCK (fs) signals that are generated by the DSP IC502, are generated by a frequency-di signalvider inside IC502 based on the 384fs
that is input to pin&c [XIN].
(2) Operation of the D-RAM CONTROLLER IC601
Operation of the D-RAM CONTROLLER IC601 when the ESP function is on is as follows. The DA DATA that is input to the D-RAM
CONTROLLER IC601 when the ESP function is on, is input to ADPCM ENCODER inside IC601, and is compressed to 5-bit data. The
DA DATA compressed to 5-bit data is sequentially stored in the D-RAM IC602 through the D-RAM CONTROLLER block inside
IC601. Then the 5-bit data that is read from the D-RAM IC602 enters the ADPCM DECODER block wher.e it is decoded to 16-bit data
The DA DATA thus decoded is output to the D/A CONVERTER IC301 with the L-ch data and the R-cionh data alternately, in synchronizat
with LRCK (L-channel/R-channel discrimination signal) that is output from pin!° [LRCO] of IC601, and also in synchronization with
BLCK (bit clock) that is output from pin!c [BCKO].
Next, operation of the D-RAM CONTROLLER IC601 when the ESP function is off, is described. When the D-RAM CONTROLLER
IC601 recognizes that the ESP function is turned off by the commands (refer to the commands described belo thew) that are sent from
system controller IC801, the switches in IC601 are activated to set the internal operation of the Discman to the pass-thrtate. Then,ough s
the DA DATA is output to the D/A CONVERTER IC301 with the L-ch data and the R-ch data alternately, in synchronization with LRCK
(L-channel/R-channel discrimination signal) that is output from pin!° [LRCO] of IC601, and also in synchronization with BLCK (bit
clock) that is output from pin!c [BCKO].
Here, the BCLK (48fs) and LRCK (fs) signals that are generated by DSP IC601, are generated by a frequencbasedy-divider inside IC601
on the 384fs signal that is input to pin9 [CLK]. The BCLK and LRCK signals that are generated inside DSP IC502 are in synchronization
with the BCLK and LRCK signals that are generated by the D-RAM CONTROLLER IC601.
¨ Interface between the system controller IC801 and the D-RAM CONTROLLER IC601
= From the system controller IC801 n D-RAM CONTROLLER IC601 =
Y Turning ON and OFF the ESP
Y Turning ON and OFF the ADPCM ENCODER block and the ADPCM DECODER block.
= From the D-RAM CONTROLLER IC601 n system controller IC801
Y Data writing status of the D-RAM IC602 (availability of the data writing area inside the D-RAM IC602, etc.)
(3) Generation of Analog Signal
The DA data that is sent to the D/A CONVERTER IC301 is D/A converted by the D/A CONVERTER inside IC301, and is output from
pin9 [LO] and pin5 [RO] as the L-ch and the R-ch analog signal.
N 25 N |
ACEC
