Pin No.Pin NameI/OFunction
81B/Cb0O
82B/Cb1O
83B/Cb2O
84B/Cb3OOutput pin of the B or Cb signal of the image data. MSB is B/Cb7. Synchronizes with
85B/Cb4ODCLK. (Not used)
86B/Cb5O
87B/Cb6O
88B/Cb7O
Dot clock (DCLK) signal pin. The DCLK frequency is normally 13.5MHz. The DCLK can
89DCLKIbe input from this pin or can be made by frequency-dividing (1/integer) the clock input
from XTL0I.
90VDD�+5V power supply
91VSS�Ground
Horizontal sync signal pin. When using the built-in sync generator, a signal is made by
92HSYNCIfrequency-dividing the dot clock (DCLK). Serves as the input when not using the built-in
sync generator.
Vertical sync signal pin. When using the built-in sync generator, a signal is made by fre-
93VSYNCI
quency-dividing the DCLK. Serves as the input when not using the built-in sync generator.
Field determination signal. Odd field correspond to OH� and even field correspond to OL�.
FIDServes as an output when the built-in sync generator is used, and as an input when not.
94I/FHREF/ Signal obtained by frequency-dividing the clock input from XTL0I or XTLI. When the
input clock is 8 fsc, it can be used as the horizontal sync signal phase comparison reference
signal.
Composite blanking signal pin. Serves as an output when the built-in sync generator is
95ICBLNKused, and as an input when not. / Signal obtained by frequency-dividing the clock input
/FSCfrom XTL0I or XTLI. When the input clock is 8 fsc, it can be used as the fsc signal.
Composite sync signal pin. A signal is made by frequency-dividing the DCLK. Cannot be
96CSYNCOinput. (Not used)
97XSGRSTISync generator reset signal pin. The signal generator is initialized by setting this pin to OL�.
98CLK0OOOutputs the frequency-divided clock of the clock input to XTL0I. The frequency dividing
ratio can be selected from 1/2, 1/4, and 1/8. (Not used)
99DOUTODigital output (Not used)
100DATOOAudio serial data output to Audio D/A converter (IC101)
101LRCOOLR clock output to Audio D/A converter (IC101)
102BCKOOBit clock output to Audio D/A converter (IC101)
103FSXIIInput 384fs (16.9344MHz) or 768fs (33.8688MHz).
104VDD�+5V power supply
105VSS�Ground
106XTL2OOCD-ROM decoder, audio decoder master clock. Input a clock to the XTL21 or connect an
oscillator between XTL2I and XTL2O. The recommended frequency is 45 MHz. This
107XTL2IIclock is for the internal circuit. Does not synchronize with inputs and outputs.
108VDD�+5V power supply
109C2POIC2 pointer input (CXD2545Q)
110LRCIILR clock input (CXD2545Q)
N 84 N |
ACEC
