58 VSSA2 Analog ground
59 RGB-GND RGB-ground
60 VSS1 0 V digital supply
61 R Analog red display output
62 G Analog green display output
63 B Analog blue display output
64 BLAN Blanking signal open drain output
65 CORQ Contrast reduction open drain output
2
66 SCL Bi-directional IC Bus clock port
2
67 SDA Bi-directional IC Bus data port
22
68 ICEN IC Bus enable
14.5.DRAM 4MX4
14.5.1.General Description
The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits
organized in a x4 con -figuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12
bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the
latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are ?don?t care?). READ and
WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a
logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling
edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior
to CAS# falling. A LATE WRITE or READ -MODIFY-WRITE occurs when WE# falls after CAS# is taken
LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of
OE#. During LATE WRITE or READ -MODIFY -WRITE cycles, OE# must be taken HIGH to disable the
data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted
while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the
accessed location. The four data inputs and the four data outputs are routed through four pins using
common I/O, and pin direction is controlled by WE# and OE#.
14.5.2.Features
? Industry-standard x4 pin out, timing, functions and packages
? State-of-the-art, high-performance, low -power CMOS silicon -gate process
? Single power supply (+3.3V ?0.3V or +5V ?10%)
? All inputs, outputs and clocks are TTL -compatible
? Refresh modes: RAS# -ONLY, HIDDEN and CAS# -BEFORE - RAS# (CBR)
? Optional Self Refresh (S) for low -power data retention
? 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)
? Extended Data-Out (EDO) PAGE MODE access cycle
? 5V-tolerant inputs and I/Os on 3.3V devices
14.5.3.Pin Assignment
Top View
*NC on 2K refresh and A11 on 4K refresh options. Note: The ?#? symbol indicates signal is active LOW.
9 |
ACEC
