14.9.SDA5550
14.9.1.General definition
The SDA5550M is a single chip teletext decoder for decoding World System Teletext data as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling
(WSS) data used for PAL plus transmissions (Line 23). The device provides an integrated general-
purpose, fully 8051-compatible Microcontroller with television specific hardware features.
Microcontroller has been enhanced to provide powerful features such as memory banking, data
pointers, and additional interrupts etc. The on -chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to 17 Kbytes. This
device can support external memory up to 1Mbyte ROM and RAM.TVTEXT Controller contains a data
slicer for VPS, WSS, PDC and TXT, an acceleration acquisition hardware module, a display generator
for Level 1.5 TXT and powerful On screen Display capabilities based on parallel attributes, and pixel
oriented characters (DRCS). The 8 bit Microcontroller operates at 360nsec cycle time (min). Controller
with dedicated hardware does most of the internal TXT acquisition processing, transfer data to/from
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external memory interface and receives/transmits data via IC-firmware user interface. SDA5550M is
realized in 0.25 micron technology with 2.5V supply voltage and 3.3V I/O compatible. The IC produces
the following input or output control signals; AGC_CON, MODE_SW, L / L?, PIP_MODS, PIP_SEL,
ON/OFF (stand -by), SC1..3_IN_AV (pin 8 information from 3 SCARTs), AFC, MUTE (to mute audio
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output IC), ICEN.
14.9.2.Features
General
? Feature selection via special function register
? Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)
? Supply Voltage 2.5 and 3.3 V
External Crystal and Programmable clock speed
Single external 6MHz crystal, all necessary clocks are generated internally
CPU clock speed selectable via special function registers.
Normal Mode 33.33 MHz CPU cl ock, Power Save mode 8.33 MHz
Microcontroller Features
? 8bit 8051 instruction set compatible CPU.
? 33.33-MHz internal clock (max.)
? 0.360ms (min.) instruction cycle
? Two 16-bit timers
? Watchdog timer
? Capture compare timer for infrared remote contro l decoding
? Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)
? ADC (4 channels, 8 bit)
? UART
Memory
? Non-multiplexed 8 -bit data and 16 ? 20 -bit address bus (ROMless Version)
? Memory banking up to 1Mbyte (Romless version)
? Up to 128 Kilobyte on Chip Program ROM
? Eight 16-bit data pointer registers (DPTR)
? 256-bytes on-chip Processor Internal RAM (IRAM)
? 128bytes extended stack memory.
? Display RAM and TXT/VPS/PDC/WSS -Acquisition-Buffer directly accessible via MOVX
? UP to 16KByte o n Chip Extended RAM (XRAM) consisting of;
- 1 Kilobyte on -chip ACQ-buffer-RAM (access via MOVX)
- 1 Kilobyte on -chip extended -RAM (XRAM, access via MOVX) for user software
- 3 Kilobyte Display Memory
Display Features
? ROM Character Set Supports all East and West European Languages in single device
? Mosaic Graphic Character Set
? Parallel Display Attributes
? Single/Double Width/Height of Characters
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ACEC
