HSYNC# // O // Digital video horizontal sync signal//
GPCI/O[25]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
124 SW //
CJTDO // O // CPU debug interface //
DACTEST[8] // I // DACs test input //
PM[10] O Probe mux data output
VSYNC# // O // Digital video vertical sync signal//
GPCI/O[24]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
122 SW //
CJTDI // I // CPU debug interface //
DACTEST[9] // I // DACs test input //
PM[9] O Probe mux data output
Digital Audio Port and CPU de-bug (9 pins)
AIN // I // Serial input of digital stereo audio //
GPCI/O[23]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
120 SW //
CJTCK // I // CPU debug interface //
PM[8] O Probe mux data output
118 AMCLK I/O Audio Master Clock input/output. 128, 192, 256 or 384 times the sampling
frequency (programmable).
S/PDIF // O // S/PDIF transmitter output for digital coded or reconstructed audio data //
110 SDATA[3] // I // SERVO channel sample data input for AFE by-pass //
PM[3] O Probe mux data output
AOUT[2,1] // O // Serial outputs of digital stereo audio //
GPCI/O[21,22] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
111,112 SW //
SDATA[4,5] I // SERVO channel sample data inputs for AFE by-pass //
PM[4,5] O Probe mux data outputs
AOUT[0] // O Serial output of digital stereo audio //
113 SDATA[6] // SERVO channel sample data input for AFE by-pass //
PM[6] Probe mux data outputs
115 ALRCLK O Digital audio left/right select output for the audio port. Square wave, at the
sampling frequency. Programmable polarity
116 ABCLK O Digital audio bit-clock output. Data on AOUT and AIN is output or latched,
respectively, with the rising or falling (programmable) edge of this clock.
GPAI/O // I/O // General purpose input/output pin, monitored/controlled by the ADP SW //
114 AOUT[3] // O // Serial output of digital stereo audio //
SDATA[7] // I // SERVO channel sample data input for AFE by-pass //
PM[7] O Probe mux data output
Loader interface, RF amplifier interface, AV bitstream interface (28 pins)
185,184 VBIASS[1,0] AI Servo analog signal reference voltage inputs
169,167 DACDRIVE[1,0] AO Drive DACs output signals
PWMACT[0] O // PWM0 output signal //
GPCI/O[39] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
187 SW //
DVDDAT[0] I // DVD-DSP data input for FE by-pass //
NRZDATA I NRZ data input for AFE and DRC by-pass
PWMACT[1] O // PWM1 output signal //
GPCI/O[40] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
7 |
ACEC
