12.27.2. Features
? PC66-, PC100-, and PC133-compliant
? Fully synchronous; all signals registered on positive edge of system clock
? Internal pipelined operation; column address can be changed every clock cycle
? Internal banks for hiding row access/precharge
? Programmable burst lengths: 1, 2, 4, 8, or full page
? Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
? Self Refresh Modes: standard and low power
? 64ms, 4,096-cycle refresh
? LVTTL-compatible inputs and outputs
? Single +3.3V ?0.3V power supply
12.27.3. Pin Descriptions
PIN NUMBERS SYMBOL TYPE DESCRIPTION
38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the output
registers.
37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW)
the CLK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks
idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE
is synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
19 CS# Input Chip Select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
38 |
ACEC
HITACHI
