A(19:0),
RAMWE, D(15:0),
RAMOE,BHEN,CPUTMS,
PortC PortB PortAROMWE, CS(1:0),CPUTCK,
(7:0)(7:0)(7:0)ROMOERD, WRCPUTDO CPUTDINMI EXTINTRxD, TxDIRRCVR (1:0)
PortD(7:0)
PortE(7:0)
PortF(7:0)2-WireProcessor ROM/16-bitWatchdog andInterruptIR
GPIOPWMUART
SerialRAM InterfaceTurbo ?PTimersControllerDecoders
Microprocessor Bus
VRGBOSD/CPU
HorizontalProcessorOSD and CPU
(23:0)Video PortMemory
ImageMemorySDRAM
Controller
ScalerInterface
Sync Decoder
OSD
Auto Image
VCLK, VPEN,Memory
Optimizer
VVS, VHS,CRISPBus
Color Space
Converter HDCPImageSDRAMMemory Out BusDisplay PortRGBE
ScalerFrame(23:0)
OSD
Buffer ImageColor Matrix,
Control &
ScalerGamma Correction
Blend
FieldCLTs, Color SpaceRGBO
Expander(23:0)
Video
DeinterlaceFrame
Buffer
GCLK, GFBK,
GPEN, GVS,Graphics PortDVS,Memory
ControllerDisplay
GHS, GSOGBusDHS,
Sync DecoderSpatialTiming
DEN,
Auto ImageMemory InGenerator
GRGBNoiseDCLK
Optimizer
(47:0)Reduction
Color SpaceMCLK DCLK UCLK
GCOAST,Converter HDCP
GREF,
Dual PLL
GBLKSPL,
Master ResetClock
GHSFOUTPW181 Internal Block
Generator
Diagram
MCLKEXT,DCLKEXT,*For internal clock generator
Reset
XI*XO*
Figure 1-1 Internal Block Diagram |